[PATCH] riscv: Align the trap handler to 64 bytes

This is required on CPUs which always operate in CLIC mode, such as the T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the trap vector base address held in mtvec is constrained to be aligned on a 64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha jlmadushan@gmail.com Signed-off-by: Samuel Holland samuel@sholland.org ---

arch/riscv/cpu/mtrap.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 6eb3ed1d5a8..5cad7b41ff7 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -26,7 +26,7 @@ .text

/* trap entry */ - .align 2 + .align 6 .global trap_entry trap_entry: addi sp, sp, -32 * REGBYTES