--- u-boot-ixp/include/asm-arm/arch-ixp/ixp425.h	2008-01-18 01:05:22.000000000 +0100
+++ u-boot-ixp-new/include/asm-arm/arch-ixp/ixp425.h	2008-02-08 18:39:16.000000000 +0100
@@ -178,6 +178,101 @@
 #define IXP425_SDR_IR     	IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
 
 /*
+ * DDR register (IXP43X - IXP46X)
+ */
+#define IXP_DDR_CFG_BASE1	0xCC00E500
+#define IXP_DDR_CFG_BASE2	0xCC00F500
+
+#define IXP_DDR_SDIR		0x00
+#define IXP_DDR_SDCR0		0x04
+#define IXP_DDR_SDCR1		0x08
+#define IXP_DDR_SDBR		0x0C
+#define IXP_DDR_SBR0		0x10
+#define IXP_DDR_SBR1		0x14
+#define IXP_DDR_S32SR		0x18
+#define IXP_DDR_ECCR		0x1C
+#define IXP_DDR_ELOG0		0x20
+#define IXP_DDR_ELOG1		0x24
+#define IXP_DDR_ECAR0		0x28
+#define IXP_DDR_ECAR1		0x2C
+#define IXP_DDR_ECTST		0x30
+#define IXP_DDR_MCISR		0x34
+#define IXP_DDR_MACR		0x38
+#define IXP_DDR_MPTCR		0x3C
+#define IXP_DDR_MPCR		0x40
+#define IXP_DDR_RFR		0x48
+#define IXP_DDR_SDPR0		0x50
+#define IXP_DDR_SDPR1		0x54
+#define IXP_DDR_SDPR2		0x58
+#define IXP_DDR_SDPR3		0x5C
+#define IXP_DDR_SDPR4		0x60
+#define IXP_DDR_SDPR5		0x64
+#define IXP_DDR_SDPR6		0x68
+#define IXP_DDR_SDPR7		0x6C
+
+#define IXP_DDR_DCALCSR		0x00
+#define IXP_DDR_RCVDLY		0x50
+#define IXP_DDR_SLVLMIX0	0x54
+#define IXP_DDR_SLVLMIX1	0x58
+#define IXP_DDR_SLVHMIX0	0x5c
+#define IXP_DDR_SLVHMIX1	0x60
+#define IXP_DDR_SLVLEN		0x64
+#define IXP_DDR_MASTMIX		0x68
+#define IXP_DDR_LEGOVERIDE	0x74
+#define IXP_DDR_DDRMISCTL	0x78
+#define IXP_DDR_HM_WRCAL	0x7c
+
+/* SDIR command values */
+#define DDR_SDIR_MODE_SET_NO_RESET	0
+#define DDR_SDIR_MODE_SET_RESET		1
+#define DDR_SDIR_PRECHARGE_ALL		2
+#define DDR_SDIR_NOP			3
+#define DDR_SDIR_EMRS_DLL_ENABLE	4
+#define DDR_SDIR_EMRS_DLL_DISABLE	5
+#define DDR_SDIR_AUTO_REFRESH		6
+#define DDR_SDIR_EMRS_2_SET_CMD		7
+#define DDR_SDIR_EMRS_3_SET_CMD		8
+
+/* SDCR0 bits */
+#define DDR_SDCR0_TRAS(x)	((x)<<28)
+#define DDR_SDCR0_TRP(x)	((x)<<24)
+#define DDR_SDCR0_TRCD(x)	((x)<<20)
+#define DDR_SDCR0_TEDP(x)	((x)<<16)
+#define DDR_SDCR0_TWL(x)	((x)<<12)
+#define DDR_SDCR0_CAS_2		(0 << 8)
+#define DDR_SDCR0_CAS_2_5	(1 << 8)
+#define DDR_SDCR0_ODT_DISABLED	(0 << 4)
+#define DDR_SDCR0_ODT_75	(1 << 4)
+#define DDR_SDCR0_ODT_150	(2 << 4)
+#define DDR_SDCR0_DDR_I		(1 << 2)
+#define DDR_SDCR0_BUS32		(1 << 1)
+
+/* SDCR1 bits */
+#define DDR_SDCR1_TRTCMD(x)	((x)<<28)
+#define DDR_SDCR1_TWTCMD(x)	((x)<<24)
+#define DDR_SDCR1_TRTW(x)	((x)<<20)
+#define DDR_SDCR1_TRFC(x)	((x)<<12)
+#define DDR_SDCR1_TWR(x)	((x)<<9)
+#define DDR_SDCR1_TRC(x)	((x)<<4)
+#define DDR_SDCR1_TWTRD(x)	((x)<<0)
+
+/* SBR0/1 bits */
+#define DDR_SBR_128Mx8		(0<<30)
+#define DDR_SBR_128Mx16		(0<<30)
+#define DDR_SBR_256Mx8		(0<<30)
+#define DDR_SBR_512Mx8		(0<<30)
+#define DDR_SBR_512Mx16		(0<<30)
+#define DDR_SBR_1Gx8		(0<<30)
+#define DDR_SBR_256Mx16		(2<<30)
+#define DDR_SBR_1Gx16		(3<<30)
+
+/* ECCR bits */
+#define DDR_ECCR_ENABLE		(1 << 3)
+#define DDR_ECCR_SBEC		(1 << 2)
+#define DDR_ECCR_MBER		(1 << 1)
+#define DDR_ECCR_SBER		(1 << 0)
+
+/*
  * UART registers
  */
 #define IXP425_UART1	0