--- u-boot-ixp/cpu/ixp/start.S 2008-01-18 01:05:22.000000000 +0100 +++ u-boot-ixp-new/cpu/ixp/start.S 2008-02-08 20:15:37.000000000 +0100 @@ -165,48 +165,309 @@ orr r1, r1, #0x80000000 str r1, [r2] #endif - mov r1, #CFG_SDR_CONFIG - ldr r2, =IXP425_SDR_CONFIG - str r1, [r2] + /* Setup DDR controller */ + ldr r0, =IXP_DDR_CFG_BASE1 + + ldr r1, =KIXRP435_SDCR0_INIT + str r1, [r0, #IXP_DDR_SDCR0] - /* disable refresh cycles */ - mov r1, #0 - ldr r3, =IXP425_SDR_REFRESH - str r1, [r3] - - /* send nop command */ - mov r1, #3 - ldr r4, =IXP425_SDR_IR - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* set SDRAM internal refresh val */ - ldr r1, =CFG_SDRAM_REFRESH_CNT - str r1, [r3] - DELAY_FOR 0x4000, r0 - - /* send precharge-all command to close all open banks */ - mov r1, #2 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* provide 8 auto-refresh cycles */ - mov r1, #4 - mov r5, #8 -111: str r1, [r4] - DELAY_FOR 0x100, r0 - subs r5, r5, #1 - bne 111b - - /* set mode register in sdram */ - mov r1, #CFG_SDR_MODE_CONFIG - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* send normal operation command */ - mov r1, #6 - str r1, [r4] - DELAY_FOR 0x4000, r0 + ldr r1, =KIXRP435_SDCR1_INIT + str r1, [r0, #IXP_DDR_SDCR1] + + mov r1, #CFG_DRAM_BASE + str r1, [r0, #IXP_DDR_SDBR] + ldr r1, [r0, #IXP_DDR_SDBR] /* readback */ + + ldr r1, =KIXRP435_SBR0_INIT + str r1, [r0, #IXP_DDR_SBR0] + ldr r1, [r0, #IXP_DDR_SBR0] + + ldr r1, =KIXRP435_SBR1_INIT + str r1, [r0, #IXP_DDR_SBR1] + ldr r1, [r0, #IXP_DDR_SBR1] + + /* Step 4. Disable refresh cycles */ + mov r1, #0 + str r1, [r0, #IXP_DDR_RFR] + + /* Step 5. Send NOP command */ + mov r1, #DDR_SDIR_NOP + str r1, [r0, #IXP_DDR_SDIR] + + /* Step 6 */ + DELAY_FOR 0x100000, r1 + + /* Step 7. Issue precharge-all command to close all open banks */ + mov r1, #DDR_SDIR_PRECHARGE_ALL + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 8. Issue an extended-mode-register2-set command */ + mov r1, #DDR_SDIR_EMRS_2_SET_CMD + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 9. Issue an extended-mode-register3-set command */ + mov r1, #DDR_SDIR_EMRS_3_SET_CMD + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 10. Issue extended mode register set to enable dll */ + mov r1, #DDR_SDIR_EMRS_DLL_ENABLE + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 11. Issue mode register set w/ DLL reset */ + mov r1, #DDR_SDIR_MODE_SET_RESET + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 12. Issue precharge-all command */ + mov r1, #DDR_SDIR_PRECHARGE_ALL + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 13. provide 2 auto-refresh cycles */ + mov r1, #DDR_SDIR_AUTO_REFRESH + mov r2, #2 + 1: + str r1, [r0, #IXP_DDR_SDIR] + ldr r3, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x800, r3 + subs r2, r2, #1 + bne 1b + + /* Step 14. Issue mode register set w/o DLL reset */ + mov r1, #DDR_SDIR_MODE_SET_NO_RESET + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x100000, r1 + + /* Step 15. Start normal operation */ + mov r1, #0xf + str r1, [r0, #IXP_DDR_SDIR] + DELAY_FOR 0x10000, r1 + + /* Step 16. Set refresh val */ + ldr r1, =KIXRP435_SDRAM_REFRESH_CNT + str r1, [r0, #IXP_DDR_RFR] + DELAY_FOR 0x100000, r1 + + /* Additional setup for SDRAM controller */ + ldr r0, =IXP_DDR_CFG_BASE2 + + ldr r1, = 0x00000004 + str r1, [r0, #IXP_DDR_RCVDLY] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x00000000 + str r1, [r0, #IXP_DDR_SLVLMIX0] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x00000000 + str r1, [r0, #IXP_DDR_SLVLMIX1] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x00000000 + str r1, [r0, #IXP_DDR_SLVHMIX0] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x00000000 + str r1, [r0, #IXP_DDR_SLVHMIX1] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x00000004 + str r1, [r0, #IXP_DDR_SLVLEN] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x00000000 + str r1, [r0, #IXP_DDR_MASTMIX] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0000000a + str r1, [r0, #IXP_DDR_LEGOVERIDE] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0002D400 + str r1, [r0, #IXP_DDR_DDRMISCTL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0000889C + str r1, [r0, #IXP_DDR_HM_WRCAL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0000889C + str r1, [r0, #IXP_DDR_HM_WRCAL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0000889C + str r1, [r0, #IXP_DDR_HM_WRCAL] + DELAY_FOR 0x100000, r1 + +#if ERROR_AFTER_FIXUP + ldr r1, = 0x0000889C + str r1, [r0, #IXP_DDR_HM_WRCAL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0000889C + str r1, [r0, #IXP_DDR_HM_WRCAL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x0000809C + str r1, [r0, #IXP_DDR_HM_WRCAL] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000006 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000106 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000206 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000306 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000406 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000506 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000606 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81000706 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002006 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002106 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002206 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002306 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002406 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002506 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002606 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81002706 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004006 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004106 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004206 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004306 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004406 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004506 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004606 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81004706 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006006 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006106 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006206 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006306 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006406 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006506 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006606 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 + + ldr r1, = 0x81006706 + str r1, [r0, #IXP_DDR_DCALCSR] + DELAY_FOR 0x100000, r1 +#endif /* copy */ mov r0, #0