Init pinmux in one shot, in order to avoid any conflicts.
Signed-off-by: Lucas Stach dev@lynxeye.de --- board/nvidia/seaboard/seaboard.c | 133 +++++++++++++++++++++++++++++++++------ include/configs/seaboard.h | 3 + include/configs/ventana.h | 3 + 3 files changed, 121 insertions(+), 18 deletions(-)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 3e33da0..b5b4b31 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2010,2011 * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2013 + * Lucas Stach * * See file CREDITS for list of people who contributed to this * project. @@ -25,7 +27,6 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/mmc.h> @@ -47,29 +48,12 @@ void gpio_early_init_uart(void) #endif
#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -static void pin_mux_mmc(void) -{ - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); - - /* For power GPIO PI6 */ - pinmux_tristate_disable(PINGRP_ATA); - /* For CD GPIO PI5 */ - pinmux_tristate_disable(PINGRP_ATC); -}
/* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n");
- /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 8-bit bus */ tegra_mmc_init(0, 8, -1, -1); @@ -87,3 +71,116 @@ void pin_mux_usb(void) /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ pinmux_tristate_disable(PINGRP_SLXK); } +static struct pingroup_config seaboard_pinmux[] = { + PINMUX_ENTRY(ATA, IDE, NORMAL, NORMAL), /* GPIO PI6 */ + PINMUX_ENTRY(ATB, SDIO4, NORMAL, NORMAL), /* SDMMC4 */ + PINMUX_ENTRY(ATC, NAND, NORMAL, NORMAL), /* NAND, GPIO PI5 */ + PINMUX_ENTRY(ATD, GMI, NORMAL, NORMAL), /* NAND, GPIO PH1,PH3 */ + PINMUX_ENTRY(ATE, GMI, NORMAL, TRISTATE), + PINMUX_ENTRY(CDEV1, PLLA_OUT, NORMAL, TRISTATE), + PINMUX_ENTRY(CDEV2, PLLP_OUT4, NORMAL, TRISTATE), + PINMUX_ENTRY(CRTP, CRT, NORMAL, TRISTATE), + PINMUX_ENTRY(CSUS, VI_SENSOR_CLK, NORMAL, TRISTATE), + PINMUX_ENTRY(DAP1, DAP1, NORMAL, TRISTATE), + PINMUX_ENTRY(DAP2, DAP2, NORMAL, TRISTATE), + PINMUX_ENTRY(DAP3, DAP3, NORMAL, TRISTATE), + PINMUX_ENTRY(DAP4, DAP4, NORMAL, TRISTATE), + PINMUX_ENTRY(DDC, I2C2, NORMAL, TRISTATE), + PINMUX_ENTRY(DTA, VI, NORMAL, TRISTATE), + PINMUX_ENTRY(DTB, VI, NORMAL, TRISTATE), + PINMUX_ENTRY(DTC, VI, NORMAL, TRISTATE), + PINMUX_ENTRY(DTD, VI, NORMAL, TRISTATE), + PINMUX_ENTRY(DTE, VI, NORMAL, TRISTATE), + PINMUX_ENTRY(DTF, I2C3, NORMAL, TRISTATE), + PINMUX_ENTRY(GMA, SDIO4, NORMAL, NORMAL), /* SDMMC4 */ + PINMUX_ENTRY(GMB, GMI, NORMAL, TRISTATE), + PINMUX_ENTRY(GMC, UARTD, NORMAL, NORMAL), /* UART D */ + PINMUX_ENTRY(GMD, SFLASH, NORMAL, TRISTATE), + PINMUX_ENTRY(GME, SDIO4, NORMAL, NORMAL), /* SDMMC4 */ + PINMUX_ENTRY(GPU, PWM, NORMAL, TRISTATE), + PINMUX_ENTRY(GPU7, RTCK, NORMAL, NORMAL), /* JTAG RTCK */ + PINMUX_ENTRY(GPV, PCIE, NORMAL, TRISTATE), + PINMUX_ENTRY(HDINT, HDMI, NORMAL, TRISTATE), + PINMUX_ENTRY(I2CP, I2C, NORMAL, TRISTATE), + PINMUX_ENTRY(IRRX, UARTB, NORMAL, TRISTATE), + PINMUX_ENTRY(IRTX, UARTB, NORMAL, TRISTATE), + PINMUX_ENTRY(KBCA, KBC, UP, NORMAL), /* KBC */ + PINMUX_ENTRY(KBCB, KBC, UP, NORMAL), /* KBC */ + PINMUX_ENTRY(KBCC, KBC, UP, NORMAL), /* KBC */ + PINMUX_ENTRY(KBCD, KBC, UP, NORMAL), /* KBC */ + PINMUX_ENTRY(KBCE, KBC, UP, NORMAL), /* KBC */ + PINMUX_ENTRY(KBCF, KBC, UP, NORMAL), /* KBC */ + PINMUX_ENTRY(LCSN, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(LD0, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD1, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD2, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD3, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD4, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD5, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD6, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD7, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD8, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD9, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD10, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD11, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD12, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD13, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD14, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD15, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD16, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LD17, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LDC, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(LDI, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LHP0, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LHP1, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LHP2, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LHS, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LM0, RSVD4, NORMAL, NORMAL), /* GPIO PW0 */ + PINMUX_ENTRY(LM1, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(LPP, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LPW0, HDMI, NORMAL, NORMAL), /* GPIO PB2 */ + PINMUX_ENTRY(LPW1, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(LPW2, HDMI, NORMAL, NORMAL), /* GPIO PC6 */ + PINMUX_ENTRY(LSC0, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LSC1, HDMI, NORMAL, TRISTATE), + PINMUX_ENTRY(LSCK, HDMI, NORMAL, TRISTATE), + PINMUX_ENTRY(LSDA, HDMI, NORMAL, TRISTATE), + PINMUX_ENTRY(LSDI, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(LSPI, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LVP0, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(LVP1, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(LVS, DISPA, NORMAL, NORMAL), /* LCD */ + PINMUX_ENTRY(OWC, RSVD2, NORMAL, TRISTATE), + PINMUX_ENTRY(PTA, RSVD4, NORMAL, TRISTATE), + PINMUX_ENTRY(RM, I2C, NORMAL, TRISTATE), + PINMUX_ENTRY(SDB, SDIO3, NORMAL, NORMAL), /* SDMMC3 */ + PINMUX_ENTRY(SDC, SDIO3, NORMAL, NORMAL), /* SDMMC3 */ + PINMUX_ENTRY(SDD, SDIO3, NORMAL, NORMAL), /* SDMMC3 */ + PINMUX_ENTRY(SDIO1, SDIO1, NORMAL, TRISTATE), + PINMUX_ENTRY(SLXA, PCIE, NORMAL, TRISTATE), + PINMUX_ENTRY(SLXC, SPDIF, NORMAL, TRISTATE), + PINMUX_ENTRY(SLXD, SPDIF, NORMAL, NORMAL), /* GPIO PD4 */ + PINMUX_ENTRY(SLXK, PCIE, NORMAL, TRISTATE), + PINMUX_ENTRY(SPDI, RSVD2, NORMAL, TRISTATE), + PINMUX_ENTRY(SPDO, RSVD2, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIA, GMI, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIB, GMI, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIC, GMI, NORMAL, TRISTATE), + PINMUX_ENTRY(SPID, SPI1, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIE, SPI1, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIF, SPI1, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIG, SPI2_ALT, NORMAL, TRISTATE), + PINMUX_ENTRY(SPIH, SPI2_ALT, NORMAL, TRISTATE), + PINMUX_ENTRY(UAA, ULPI, NORMAL, TRISTATE), + PINMUX_ENTRY(UAB, ULPI, NORMAL, TRISTATE), + PINMUX_ENTRY(UAC, RSVD2, NORMAL, TRISTATE), + PINMUX_ENTRY(UAD, UARTB, NORMAL, TRISTATE), + PINMUX_ENTRY(UCA, UARTC, NORMAL, TRISTATE), + PINMUX_ENTRY(UCB, UARTC, NORMAL, TRISTATE), + PINMUX_ENTRY(UDA, ULPI, NORMAL, TRISTATE), +}; + +void pinmux_init(void) +{ + pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux)); +} diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index de0c777..4e3bf1c 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -35,6 +35,9 @@
#include "tegra20-common.h"
+/* Enable tablebased pinmux */ +#define CONFIG_TEGRA_TABLEBASED_PINMUX + /* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard #define CONFIG_OF_CONTROL diff --git a/include/configs/ventana.h b/include/configs/ventana.h index b55ebc9..9a023b0 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -27,6 +27,9 @@ #include <asm/sizes.h> #include "tegra20-common.h"
+/* Enable tablebased pinmux */ +#define CONFIG_TEGRA_TABLEBASED_PINMUX + /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra20-ventana #define CONFIG_OF_CONTROL