Add support to common commands, features, image format, and common headers.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- common/cmd_bdinfo.c | 26 ++++++ common/cmd_bootm.c | 2 + common/image.c | 1 + include/common.h | 13 +++ include/image.h | 5 + include/nds32_common.h | 203 ++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 250 insertions(+), 0 deletions(-) create mode 100644 include/nds32_common.h
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index fbe73f1..b65797b 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -348,6 +348,32 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
+#elif defined(CONFIG_NDS32) + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + bd_t *bd = gd->bd; + + print_num ("arch_number", bd->bi_arch_number); + print_num ("env_t", (ulong)bd->bi_env); + print_num ("boot_params", (ulong)bd->bi_boot_params); + + for (i=0; i<CONFIG_NR_DRAM_BANKS; ++i) { + print_num("DRAM bank", i); + print_num("-> start", bd->bi_dram[i].start); + print_num("-> size", bd->bi_dram[i].size); + } + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif + printf ("baudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else #error "a case for this architecture does not exist!" #endif diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index adfa6cd..7fc2284 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -182,6 +182,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os"))); #define IH_INITRD_ARCH IH_ARCH_SH #elif defined(__sparc__) #define IH_INITRD_ARCH IH_ARCH_SPARC +#elif defined(__nds32__) + #define IH_INITRD_ARCH IH_ARCH_NDS32 #else # error Unknown CPU type #endif diff --git a/common/image.c b/common/image.c index 6d8833e..ce968e2 100644 --- a/common/image.c +++ b/common/image.c @@ -93,6 +93,7 @@ static table_entry_t uimage_arch[] = { { IH_ARCH_SPARC64, "sparc64", "SPARC 64 Bit", }, { IH_ARCH_BLACKFIN, "blackfin", "Blackfin", }, { IH_ARCH_AVR32, "avr32", "AVR32", }, + { IH_ARCH_NDS32, "nds32", "NDS32", }, { -1, "", "", }, };
diff --git a/include/common.h b/include/common.h index eddec22..8d9c36d 100644 --- a/include/common.h +++ b/include/common.h @@ -43,6 +43,9 @@ typedef volatile unsigned char vu_char; #if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) #include <pci.h> #endif +#if defined(CONFIG_NDS32) +#include <nds32_common.h> /* should be reference to <asm/somefile.h> */ +#endif #if defined(CONFIG_8xx) #include <asm/8xx_immap.h> #if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ @@ -274,6 +277,12 @@ void forceenv (char *, char *); #ifdef CONFIG_I386 /* x86 version to be fixed! */ # include <asm/u-boot-i386.h> #endif /* CONFIG_I386 */ +#ifdef CONFIG_NDS32 +# include <asm/mach-types.h> +# include <asm/setup.h> +# include <asm/u-boot-nds32.h> /* NDS32 version to be fixed! */ +# include <asm/andesboot.h> +#endif /* CONFIG_NDS32 */
#ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); @@ -729,10 +738,14 @@ int cpu_release(int nr, int argc, char * const argv[]); #define CONFIG_HAS_POST #endif
+/* CONFIG_INIT_CRITICAL is necessay to run cpu_init_crit in start.s, + or exception would rise*/ +#ifndef __nds32__ #ifdef CONFIG_INIT_CRITICAL #error CONFIG_INIT_CRITICAL is deprecated! #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif +#endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
diff --git a/include/image.h b/include/image.h index bcc08d1..17a673d 100644 --- a/include/image.h +++ b/include/image.h @@ -105,6 +105,7 @@ #define IH_ARCH_BLACKFIN 16 /* Blackfin */ #define IH_ARCH_AVR32 17 /* AVR32 */ #define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */ +#define IH_ARCH_NDS32 19 /* ANDES Technology - nds32 */
/* * Image Types @@ -500,6 +501,8 @@ static inline int image_check_target_arch (const image_header_t *hdr) if (!image_check_arch (hdr, IH_ARCH_SH)) #elif defined(__sparc__) if (!image_check_arch (hdr, IH_ARCH_SPARC)) +#elif defined(__nds32__) + if (!image_check_arch (hdr, IH_ARCH_NDS32)) #else # error Unknown CPU type #endif @@ -652,6 +655,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node) if (!fit_image_check_arch (fdt, node, IH_ARCH_SH)) #elif defined(__sparc__) if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC)) +#elif defined(__nds32__) + if (!fit_image_check_arch (fdt, node, IH_ARCH_NDS32)) #else # error Unknown CPU type #endif diff --git a/include/nds32_common.h b/include/nds32_common.h new file mode 100644 index 0000000..324e671 --- /dev/null +++ b/include/nds32_common.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __NDS32_COMMON_H +#define __NDS32_COMMON_H + +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/**************************************************************************** + * Copyright Faraday Technology Corp 2002-2003. All rights reserved. * + *--------------------------------------------------------------------------* + * Name:cpe.s * + * Description: NDS32_COMMON board specfic define * + * (renamed CPE_ (COMMON PLATFORM ENVIRONMENT) to NDS32_COMMON_ ) * + * Author: Fred Chien * + * Update: Macpaul Lin macpaul@andestech.com * + * *************************************************************************/ + +/* + * NDS32_COMMON address map; + * + * +========================================== + * 0x00000000 | ROM + * | + * 0x00080000 |========================================== + * | SRAM + * |========================================== + * 0x10000000 | SDRAM + * 0x8FFFFFFF | + * |========================================== + * 0x90000000 |Controller's reg + * | + * |0x90100000 Arbiter/Decoder + * |0x90200000 SRAM controller reg + * |0x902ffffc Debug Numberic LED + * |0x90900000 SDRAM controller reg + * |0x90400000 DMA controller reg + * |0x90500000 AHB2APB bridge + * |0x90600000 Reserved + * |0x91000000-91F00000 DMA0-DMA15 Device; + * |0x92400000 DSP + * |0x92500000 Reserved + * |0x96500000 LCD + * |0x96600000 Bluetooth + * |0x96700000 MAC + * |0x96800000 PCI + * |0x96900000 USB2.0 host + * |0x98000000-9AFFFFFF APB Device + * 0x98000000 |========================================== + * | APB Device's Reg + * | + * |0x98000000 Reserved + * |0x98100000 Power Managemnet + * |0x98200000 UART1 + * |0x98300000 UART2/IrDA + * |0x98400000 Timer + * |0x98500000 Watchdog Timer + * |0x98600000 RTC + * |0x98700000 GPIO + * |0x98800000 INTC + * |0x98900000 UART3 + * |0x98A00000 I2C + * |0x98B00000 SSP1 + * |0x98C00000 USB Device + * |0x98D00000 Compact Flash + * |0x98E00000 Secure Digital + * |0x98F00000 SMC + * |0x99000000 MS + * |0x99100000 SCI + * |0x99200000 ECP/EPP + * |0x99300000 KBC + * |0x99400000 I2S + * |0x99500000 AC97 + * |0x99600000 SSP2 + * |0x99700000 Mouse + * |0x9AFFFFFF Reserved + * | + * +========================================== + */ + +/* =============================================================================== + * NDS32_COMMON definitions + * =============================================================================== + * ------------------------------------------------------------------------------- + * Memory definitions + * ------------------------------------------------------------------------------- + */ + +#define NDS32_COMMON_ROM_LO 0x00000000 +#define NDS32_COMMON_ROM_HI 0x80000000 +#define NDS32_COMMON_ROM_BASE NDS32_COMMON_ROM_HI /* remap position */ +#define NDS32_COMMON_ROM_SIZE SZ_128K + +#define NDS32_COMMON_SRAM_LO 0x00080000 +#define NDS32_COMMON_SRAM_HI 0x80080000 +#define NDS32_COMMON_SRAM_BASE NDS32_COMMON_SRAM_HI /* remap position */ +#define NDS32_COMMON_SRAM_SIZE SZ_512K + +#define NDS32_COMMON_SDRAM_LO 0x00000000 +#define NDS32_COMMON_SDRAM_HI 0x10000000 +#define NDS32_COMMON_SDRAM_BASE NDS32_COMMON_SDRAM_LO /* remap postion */ +#define NDS32_COMMON_SDRAM_SIZE SZ_128M + +/* ------------------------------------------------------------------------------- + * NDS32_COMMON system registers + * ------------------------------------------------------------------------------- + */ + +#define NDS32_COMMON_DECODER_BASE 0x90100000 +#define NDS32_COMMON_SRAMC_BASE 0x90200000 + +#define SRAMBANK_BASE NDS32_COMMON_SRAM_LO + +#define NDS32_COMMON_SDRAMC_BASE 0x90300000 +#define NDS32_COMMON_DMA_BASE 0x90400000 +#define NDS32_COMMON_APB_BASE 0x90500000 + + +/* ------------------------------------------------------------------------------- + * APB Device definitions + * ------------------------------------------------------------------------------- + */ + +#define NDS32_COMMON_PWM_BASE 0x98100000 /* Power Management */ +#define NDS32_COMMON_UART1_BASE 0x99600000 /* UART 1 */ +#define NDS32_COMMON_UART2_BASE 0x98300000 /* UART 2/IrDA */ +#define NDS32_COMMON_CT_BASE 0x98400000 /* Counter/Timers */ +#define NDS32_COMMON_WATCHDOG_BASE 0x98500000 /* Watchdog Timer */ +#define NDS32_COMMON_RTC_BASE 0x98600000 /* Real Time Clock */ +#define NDS32_COMMON_GPIO_BASE 0x98700000 /* GPIO */ +#define NDS32_COMMON_IC_BASE 0x98800000 /* Interrupt Controller */ +#define NDS32_COMMON_UART3_BASE 0x98200000 /* UART 3 */ +#define NDS32_COMMON_I2C_BASE 0x98A00000 /* I2C */ +#define NDS32_COMMON_SSP1_BASE 0x98B00000 /* SSP1 */ +#define NDS32_COMMON_CF_BASE 0x98D00000 /* CF */ +#define NDS32_COMMON_SD_BASE 0x98E00000 /* SD */ +#define NDS32_COMMON_SMMC_BASE 0x98F00000 /* SMC */ +#define NDS32_COMMON_I2S_BASE 0x99400000 /* I2S */ +#define NDS32_COMMON_AC97_BASE 0x99500000 /* AC97 */ +#define NDS32_COMMON_SSP2_BASE 0x99600000 /* SSP2 */ +#define NDS32_COMMON_KBD_BASE 0x99300000 /* Keyboard */ +#define NDS32_COMMON_MOUSE_BASE 0x99b00000 /* Mouse */ +#define NDS32_COMMON_MMSC_BASE 0x99900000 /* Memory Stick */ + +#define NDS32_COMMON_TIMER1_BASE NDS32_COMMON_CT_BASE +#define NDS32_COMMON_TIMER2_BASE (NDS32_COMMON_CT_BASE + 0x10) +#define NDS32_COMMON_TIMER3_BASE (NDS32_COMMON_CT_BASE + 0x20) + +#define SYS_CLK CONFIG_SYS_CLK_FREQ +#define AHB_CLK SYS_CLK +#define MAX_TIMER 3 +#define APB_CLK (SYS_CLK / 2) +#define DEFAULT_TICK 1 +#define PCLK_HZ (SYS_CLK/4) + +#define NDS32_COMMON_UART_CLOCK UART_CLOCK +#define NDS32_COMMON_BAUD_115200 (NDS32_COMMON_UART_CLOCK /1843200) +#define NDS32_COMMON_BAUD_57600 (NDS32_COMMON_UART_CLOCK /921600) +#define NDS32_COMMON_BAUD_38400 (NDS32_COMMON_UART_CLOCK /614400) +#define NDS32_COMMON_BAUD_19200 (NDS32_COMMON_UART_CLOCK /307200) +#define NDS32_COMMON_BAUD_14400 (NDS32_COMMON_UART_CLOCK /230400) +#define NDS32_COMMON_BAUD_9600 (NDS32_COMMON_UART_CLOCK /153600) + +#define HOST_COMPORT NDS32_COMMON_UART1_BASE +#define HOST_IRQBIT_NUMBER IRQ_UART1 + +/* Default port for use by Operating System or program */ +#define OS_COMPORT NDS32_COMMON_UART2_BASE +#define OS_IRQBIT_NUMBER IRQ_UART2 + +#define DEBUG_COMPORT OS_COMPORT +#define DEBUG_IRQBIT OS_IRQBIT +#define MAX_UART_NUM 2 + +/* Values to set given baud rates */ +#define DEFAULT_HOST_BAUD NDS32_COMMON_BAUD_9600 + +/* NUMBERIC DISPLAY LED */ +#define NDS32_COMMON_DBG_ALPHA 0x902ffffc + +#endif