These are still non-generic boards.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Ajay Bhargav ajay.bhargav@einfochips.com ---
arch/arm/Kconfig | 10 - arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/armada100/Makefile | 9 - arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 --- arch/arm/cpu/arm926ejs/armada100/dram.c | 116 ---- arch/arm/cpu/arm926ejs/armada100/timer.c | 194 ------ arch/arm/include/asm/arch-armada100/armada100.h | 60 -- arch/arm/include/asm/arch-armada100/config.h | 42 -- arch/arm/include/asm/arch-armada100/cpu.h | 162 ----- arch/arm/include/asm/arch-armada100/gpio.h | 32 - arch/arm/include/asm/arch-armada100/mfp.h | 80 --- arch/arm/include/asm/arch-armada100/spi.h | 79 --- .../include/asm/arch-armada100/utmi-armada100.h | 63 -- board/Marvell/aspenite/Kconfig | 15 - board/Marvell/aspenite/MAINTAINERS | 6 - board/Marvell/aspenite/Makefile | 10 - board/Marvell/aspenite/aspenite.c | 43 -- board/Marvell/gplugd/Kconfig | 15 - board/Marvell/gplugd/MAINTAINERS | 6 - board/Marvell/gplugd/Makefile | 15 - board/Marvell/gplugd/gplugd.c | 130 ---- configs/aspenite_defconfig | 2 - configs/gplugd_defconfig | 2 - doc/README.scrapyard | 2 + drivers/net/Makefile | 1 - drivers/net/armada100_fec.c | 726 --------------------- drivers/net/armada100_fec.h | 209 ------ drivers/spi/Makefile | 1 - drivers/spi/armada100_spi.c | 203 ------ drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-armada100.c | 48 -- drivers/usb/host/utmi-armada100.c | 80 --- include/configs/aspenite.h | 55 -- include/configs/gplugd.h | 134 ---- include/netdev.h | 1 - 35 files changed, 2 insertions(+), 2643 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c delete mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c delete mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c delete mode 100644 arch/arm/include/asm/arch-armada100/armada100.h delete mode 100644 arch/arm/include/asm/arch-armada100/config.h delete mode 100644 arch/arm/include/asm/arch-armada100/cpu.h delete mode 100644 arch/arm/include/asm/arch-armada100/gpio.h delete mode 100644 arch/arm/include/asm/arch-armada100/mfp.h delete mode 100644 arch/arm/include/asm/arch-armada100/spi.h delete mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h delete mode 100644 board/Marvell/aspenite/Kconfig delete mode 100644 board/Marvell/aspenite/MAINTAINERS delete mode 100644 board/Marvell/aspenite/Makefile delete mode 100644 board/Marvell/aspenite/aspenite.c delete mode 100644 board/Marvell/gplugd/Kconfig delete mode 100644 board/Marvell/gplugd/MAINTAINERS delete mode 100644 board/Marvell/gplugd/Makefile delete mode 100644 board/Marvell/gplugd/gplugd.c delete mode 100644 configs/aspenite_defconfig delete mode 100644 configs/gplugd_defconfig delete mode 100644 drivers/net/armada100_fec.c delete mode 100644 drivers/net/armada100_fec.h delete mode 100644 drivers/spi/armada100_spi.c delete mode 100644 drivers/usb/host/ehci-armada100.c delete mode 100644 drivers/usb/host/utmi-armada100.c delete mode 100644 include/configs/aspenite.h delete mode 100644 include/configs/gplugd.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3ec570b..702302f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -109,14 +109,6 @@ config TARGET_INTEGRATORCP_CM926EJS bool "Support integratorcp_cm926ejs" select CPU_ARM926EJS
-config TARGET_ASPENITE - bool "Support aspenite" - select CPU_ARM926EJS - -config TARGET_GPLUGD - bool "Support gplugd" - select CPU_ARM926EJS - config TARGET_AFEB9260 bool "Support afeb9260" select CPU_ARM926EJS @@ -825,9 +817,7 @@ source "board/BuR/tseries/Kconfig" source "board/BuS/eb_cpux9k2/Kconfig" source "board/BuS/vl_ma2sc/Kconfig" source "board/CarMediaLab/flea3/Kconfig" -source "board/Marvell/aspenite/Kconfig" source "board/Marvell/db-mv784mp-gp/Kconfig" -source "board/Marvell/gplugd/Kconfig" source "board/afeb9260/Kconfig" source "board/altera/socfpga/Kconfig" source "board/armadeus/apf27/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 38ab0d4..f6000af 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -14,7 +14,6 @@ extra-y := endif endif
-obj-$(CONFIG_ARMADA100) += armada100/ obj-$(CONFIG_AT91FAMILY) += at91/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ obj-$(CONFIG_KIRKWOOD) += kirkwood/ diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile deleted file mode 100644 index fca98ef..0000000 --- a/arch/arm/cpu/arm926ejs/armada100/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2010 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c deleted file mode 100644 index 8b02d0b..0000000 --- a/arch/arm/cpu/arm926ejs/armada100/cpu.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> - -#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) -#define SET_MRVL_ID (1<<8) -#define L2C_RAM_SEL (1<<4) - -int arch_cpu_init(void) -{ - u32 val; - struct armd1cpu_registers *cpuregs = - (struct armd1cpu_registers *) ARMD1_CPU_BASE; - - struct armd1apb1_registers *apb1clkres = - (struct armd1apb1_registers *) ARMD1_APBC1_BASE; - - struct armd1mpmu_registers *mpmu = - (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; - - /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */ - val = readl(&cpuregs->cpu_conf); - val = val | SET_MRVL_ID; - writel(val, &cpuregs->cpu_conf); - - /* Enable Clocks for all hardware units */ - writel(0xFFFFFFFF, &mpmu->acgr); - - /* Turn on AIB and AIB-APB Functional clock */ - writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib); - - /* ensure L2 cache is not mapped as SRAM */ - val = readl(&cpuregs->cpu_conf); - val = val & ~(L2C_RAM_SEL); - writel(val, &cpuregs->cpu_conf); - - /* Enable GPIO clock */ - writel(APBC_APBCLK, &apb1clkres->gpio); - -#ifdef CONFIG_I2C_MV - /* Enable general I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); - writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); - - /* Enable power I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); - writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); -#endif - - /* - * Enable Functional and APB clock at 14.7456MHz - * for configured UART console - */ -#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE) - writel(UARTCLK14745KHZ, &apb1clkres->uart3); -#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE) - writel(UARTCLK14745KHZ, &apb1clkres->uart2); -#else - writel(UARTCLK14745KHZ, &apb1clkres->uart1); -#endif - icache_enable(); - - return 0; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 id; - struct armd1cpu_registers *cpuregs = - (struct armd1cpu_registers *) ARMD1_CPU_BASE; - - id = readl(&cpuregs->chip_id); - printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); - return 0; -} -#endif - -#ifdef CONFIG_I2C_MV -void i2c_clk_enable(void) -{ -} -#endif diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c deleted file mode 100644 index 8d7c71f..0000000 --- a/arch/arm/cpu/arm926ejs/armada100/dram.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com, - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/armada100.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * ARMADA100 DRAM controller supports upto 8 banks - * for chip select 0 and 1 - */ - -/* - * DDR Memory Control Registers - * Refer Datasheet Appendix A.17 - */ -struct armd1ddr_map_registers { - u32 cs; /* Memory Address Map Register -CS */ - u32 pad[3]; -}; - -struct armd1ddr_registers { - u8 pad[0x100 - 0x000]; - struct armd1ddr_map_registers mmap[2]; -}; - -/* - * armd1_sdram_base - reads SDRAM Base Address Register - */ -u32 armd1_sdram_base(int chip_sel) -{ - struct armd1ddr_registers *ddr_regs = - (struct armd1ddr_registers *)ARMD1_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; - return result; -} - -/* - * armd1_sdram_size - reads SDRAM size - */ -u32 armd1_sdram_size(int chip_sel) -{ - struct armd1ddr_registers *ddr_regs = - (struct armd1ddr_registers *)ARMD1_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs); - result = (result >> 16) & 0xF; - if (result < 0x7) { - printf("Unknown DRAM Size\n"); - return -1; - } else { - return ((0x8 << (result - 0x7)) * 1024 * 1024); - } -} - -#ifndef CONFIG_SYS_BOARD_DRAM_INIT -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = armd1_sdram_base(i); - gd->bd->bi_dram[i].size = armd1_sdram_size(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -void dram_init_banksize(void) -{ - dram_init(); -} -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c deleted file mode 100644 index bbd0505..0000000 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> - -/* - * Timer registers - * Refer Section A.6 in Datasheet - */ -struct armd1tmr_registers { - u32 clk_ctrl; /* Timer clk control reg */ - u32 match[9]; /* Timer match registers */ - u32 count[3]; /* Timer count registers */ - u32 status[3]; - u32 ie[3]; - u32 preload[3]; /* Timer preload value */ - u32 preload_ctrl[3]; - u32 wdt_match_en; - u32 wdt_match_r; - u32 wdt_val; - u32 wdt_sts; - u32 icr[3]; - u32 wdt_icr; - u32 cer; /* Timer count enable reg */ - u32 cmr; - u32 ilr[3]; - u32 wcr; - u32 wfar; - u32 wsar; - u32 cvwr; -}; - -#define TIMER 0 /* Use TIMER 0 */ -/* Each timer has 3 match registers */ -#define MATCH_CMP(x) ((3 * TIMER) + x) -#define TIMER_LOAD_VAL 0xffffffff -#define COUNT_RD_REQ 0x1 - -DECLARE_GLOBAL_DATA_PTR; -/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ - -/* For preventing risk of instability in reading counter value, - * first set read request to register cvwr and then read same - * register after it captures counter value. - */ -ulong read_timer(void) -{ - struct armd1tmr_registers *armd1timers = - (struct armd1tmr_registers *) ARMD1_TIMER_BASE; - volatile int loop=100; - - writel(COUNT_RD_REQ, &armd1timers->cvwr); - while (loop--); - return(readl(&armd1timers->cvwr)); -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (now >= gd->arch.tbl) { - /* normal mode */ - gd->arch.tbu += now - gd->arch.tbl; - } else { - /* we have an overflow ... */ - gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; - } - gd->arch.tbl = now; - - return gd->arch.tbu; -} - -ulong get_timer(ulong base) -{ - return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - - base); -} - -void __udelay(unsigned long usec) -{ - ulong delayticks; - ulong endtime; - - delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); - endtime = get_timer_masked() + delayticks; - - while (get_timer_masked() < endtime); -} - -/* - * init the Timer - */ -int timer_init(void) -{ - struct armd1apb1_registers *apb1clkres = - (struct armd1apb1_registers *) ARMD1_APBC1_BASE; - struct armd1tmr_registers *armd1timers = - (struct armd1tmr_registers *) ARMD1_TIMER_BASE; - - /* Enable Timer clock at 3.25 MHZ */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); - - /* load value into timer */ - writel(0x0, &armd1timers->clk_ctrl); - /* Use Timer 0 Match Resiger 0 */ - writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]); - /* Preload value is 0 */ - writel(0x0, &armd1timers->preload[TIMER]); - /* Enable match comparator 0 for Timer 0 */ - writel(0x1, &armd1timers->preload_ctrl[TIMER]); - - /* Enable timer 0 */ - writel(0x1, &armd1timers->cer); - /* init the gd->arch.tbu and gd->arch.tbl value */ - gd->arch.tbl = read_timer(); - gd->arch.tbu = 0; - - return 0; -} - -#define MPMU_APRR_WDTR (1<<4) -#define TMR_WFAR 0xbaba /* WDT Register First key */ -#define TMP_WSAR 0xeb10 /* WDT Register Second key */ - -/* - * This function uses internal Watchdog Timer - * based reset mechanism. - * Steps to write watchdog registers (protected access) - * 1. Write key value to TMR_WFAR reg. - * 2. Write key value to TMP_WSAR reg. - * 3. Perform write operation. - */ -void reset_cpu (unsigned long ignored) -{ - struct armd1mpmu_registers *mpmu = - (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; - struct armd1tmr_registers *armd1timers = - (struct armd1tmr_registers *) ARMD1_TIMER_BASE; - u32 val; - - /* negate hardware reset to the WDT after system reset */ - val = readl(&mpmu->aprr); - val = val | MPMU_APRR_WDTR; - writel(val, &mpmu->aprr); - - /* reset/enable WDT clock */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr); - readl(&mpmu->wdtpcr); - writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); - readl(&mpmu->wdtpcr); - - /* clear previous WDT status */ - writel(TMR_WFAR, &armd1timers->wfar); - writel(TMP_WSAR, &armd1timers->wsar); - writel(0, &armd1timers->wdt_sts); - - /* set match counter */ - writel(TMR_WFAR, &armd1timers->wfar); - writel(TMP_WSAR, &armd1timers->wsar); - writel(0xf, &armd1timers->wdt_match_r); - - /* enable WDT reset */ - writel(TMR_WFAR, &armd1timers->wfar); - writel(TMP_WSAR, &armd1timers->wsar); - writel(0x3, &armd1timers->wdt_match_en); - - while(1); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h deleted file mode 100644 index d9feb16..0000000 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_ARMADA100_H -#define _ASM_ARCH_ARMADA100_H - -#if defined (CONFIG_ARMADA100) - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Fast Ethernet Controller Clock register definition */ -#define FE_CLK_RST 0x1 -#define FE_CLK_ENA 0x8 - -/* SSP2 Clock Control */ -#define SSP2_APBCLK 0x01 -#define SSP2_FNCLK 0x02 - -/* USB Clock/reset control bits */ -#define USB_SPH_AXICLK_EN 0x10 -#define USB_SPH_AXI_RST 0x02 - -/* MPMU Clocks */ -#define APB2_26M_EN (1 << 20) -#define AP_26M (1 << 4) - -/* Register Base Addresses */ -#define ARMD1_DRAM_BASE 0xB0000000 -#define ARMD1_FEC_BASE 0xC0800000 -#define ARMD1_TIMER_BASE 0xD4014000 -#define ARMD1_APBC1_BASE 0xD4015000 -#define ARMD1_APBC2_BASE 0xD4015800 -#define ARMD1_UART1_BASE 0xD4017000 -#define ARMD1_UART2_BASE 0xD4018000 -#define ARMD1_GPIO_BASE 0xD4019000 -#define ARMD1_SSP1_BASE 0xD401B000 -#define ARMD1_SSP2_BASE 0xD401C000 -#define ARMD1_MFPR_BASE 0xD401E000 -#define ARMD1_SSP3_BASE 0xD401F000 -#define ARMD1_SSP4_BASE 0xD4020000 -#define ARMD1_SSP5_BASE 0xD4021000 -#define ARMD1_UART3_BASE 0xD4026000 -#define ARMD1_MPMU_BASE 0xD4050000 -#define ARMD1_USB_HOST_BASE 0xD4209000 -#define ARMD1_APMU_BASE 0xD4282800 -#define ARMD1_CPU_BASE 0xD4282C00 - -#endif /* CONFIG_ARMADA100 */ -#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h deleted file mode 100644 index e062da1..0000000 --- a/arch/arm/include/asm/arch-armada100/config.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen leiwen@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file should be included in board config header file. - * - * It supports common definitions for Armada100 platform - */ - -#ifndef _ARMD1_CONFIG_H -#define _ARMD1_CONFIG_H - -#include <asm/arch/armada100.h> -/* default Dcache Line length for armada100 */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE ARMD1_MFPR_BASE -#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ -/* - * I2C definition - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_NUM 2 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000} -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 0 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -#endif /* _ARMD1_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h deleted file mode 100644 index c1f190d..0000000 --- a/arch/arm/include/asm/arch-armada100/cpu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com, Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ARMADA100CPU_H -#define _ARMADA100CPU_H - -#include <asm/io.h> -#include <asm/system.h> - -/* - * Main Power Management (MPMU) Registers - * Refer Datasheet Appendix A.8 - */ -struct armd1mpmu_registers { - u8 pad0[0x08 - 0x00]; - u32 fccr; /*0x0008*/ - u32 pocr; /*0x000c*/ - u32 posr; /*0x0010*/ - u32 succr; /*0x0014*/ - u8 pad1[0x030 - 0x014 - 4]; - u32 gpcr; /*0x0030*/ - u8 pad2[0x200 - 0x030 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad3[0x1000 - 0x200 - 4]; - u32 apcr; /*0x1000*/ - u32 apsr; /*0x1004*/ - u8 pad4[0x1020 - 0x1004 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ - u32 arsr; /*0x1028*/ -}; - -/* - * Application Subsystem Power Management - * Refer Datasheet Appendix A.9 - */ -struct armd1apmu_registers { - u32 pcr; /* 0x000 */ - u32 ccr; /* 0x004 */ - u32 pad1; - u32 ccsr; /* 0x00C */ - u32 fc_timer; /* 0x010 */ - u32 pad2; - u32 ideal_cfg; /* 0x018 */ - u8 pad3[0x04C - 0x018 - 4]; - u32 lcdcrc; /* 0x04C */ - u32 cciccrc; /* 0x050 */ - u32 sd1crc; /* 0x054 */ - u32 sd2crc; /* 0x058 */ - u32 usbcrc; /* 0x05C */ - u32 nfccrc; /* 0x060 */ - u32 dmacrc; /* 0x064 */ - u32 pad4; - u32 buscrc; /* 0x06C */ - u8 pad5[0x07C - 0x06C - 4]; - u32 wake_clr; /* 0x07C */ - u8 pad6[0x090 - 0x07C - 4]; - u32 core_status; /* 0x090 */ - u32 rfsc; /* 0x094 */ - u32 imr; /* 0x098 */ - u32 irwc; /* 0x09C */ - u32 isr; /* 0x0A0 */ - u8 pad7[0x0B0 - 0x0A0 - 4]; - u32 mhst; /* 0x0B0 */ - u32 msr; /* 0x0B4 */ - u8 pad8[0x0C0 - 0x0B4 - 4]; - u32 msst; /* 0x0C0 */ - u32 pllss; /* 0x0C4 */ - u32 smb; /* 0x0C8 */ - u32 gccrc; /* 0x0CC */ - u8 pad9[0x0D4 - 0x0CC - 4]; - u32 smccrc; /* 0x0D4 */ - u32 pad10; - u32 xdcrc; /* 0x0DC */ - u32 sd3crc; /* 0x0E0 */ - u32 sd4crc; /* 0x0E4 */ - u8 pad11[0x0F0 - 0x0E4 - 4]; - u32 cfcrc; /* 0x0F0 */ - u32 mspcrc; /* 0x0F4 */ - u32 cmucrc; /* 0x0F8 */ - u32 fecrc; /* 0x0FC */ - u32 pciecrc; /* 0x100 */ - u32 epdcrc; /* 0x104 */ -}; - -/* - * APB1 Clock Reset/Control Registers - * Refer Datasheet Appendix A.10 - */ -struct armd1apb1_registers { - u32 uart1; /*0x000*/ - u32 uart2; /*0x004*/ - u32 gpio; /*0x008*/ - u32 pwm1; /*0x00c*/ - u32 pwm2; /*0x010*/ - u32 pwm3; /*0x014*/ - u32 pwm4; /*0x018*/ - u8 pad0[0x028 - 0x018 - 4]; - u32 rtc; /*0x028*/ - u32 twsi0; /*0x02c*/ - u32 kpc; /*0x030*/ - u32 timers; /*0x034*/ - u8 pad1[0x03c - 0x034 - 4]; - u32 aib; /*0x03c*/ - u32 sw_jtag; /*0x040*/ - u32 timer1; /*0x044*/ - u32 onewire; /*0x048*/ - u8 pad2[0x050 - 0x048 - 4]; - u32 asfar; /*0x050 AIB Secure First Access Reg*/ - u32 assar; /*0x054 AIB Secure Second Access Reg*/ - u8 pad3[0x06c - 0x054 - 4]; - u32 twsi1; /*0x06c*/ - u32 uart3; /*0x070*/ - u8 pad4[0x07c - 0x070 - 4]; - u32 timer2; /*0x07C*/ - u8 pad5[0x084 - 0x07c - 4]; - u32 ac97; /*0x084*/ -}; - -/* -* APB2 Clock Reset/Control Registers -* Refer Datasheet Appendix A.11 -*/ -struct armd1apb2_registers { - u32 pad1[0x01C - 0x000]; - u32 ssp1_clkrst; /* 0x01C */ - u32 ssp2_clkrst; /* 0x020 */ - u32 pad2[0x04C - 0x020 - 4]; - u32 ssp3_clkrst; /* 0x04C */ - u32 pad3[0x058 - 0x04C - 4]; - u32 ssp4_clkrst; /* 0x058 */ - u32 ssp5_clkrst; /* 0x05C */ -}; - -/* - * CPU Interface Registers - * Refer Datasheet Appendix A.2 - */ -struct armd1cpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 armd1_sdram_base(int); -u32 armd1_sdram_size(int); - -#endif /* _ARMADA100CPU_H */ diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h deleted file mode 100644 index 4927abe..0000000 --- a/arch/arm/include/asm/arch-armada100/gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_GPIO_H -#define _ASM_ARCH_GPIO_H - -#include <asm/types.h> -#include <asm/arch/armada100.h> - -#define GPIO_HIGH 1 -#define GPIO_LOW 0 - -#define GPIO_TO_REG(gp) (gp >> 5) -#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) -#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) - -static inline void *get_gpio_base(int bank) -{ - const unsigned int offset[4] = {0, 4, 8, 0x100}; - /* gpio register bank offset - refer Appendix A.36 */ - return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); -} - -#endif /* _ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h deleted file mode 100644 index b918239..0000000 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h - * (C) Copyright 2007 - * Marvell Semiconductor <www.marvell.com> - * 2007-08-21: eric miao eric.miao@marvell.com - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARMADA100_MFP_H -#define __ARMADA100_MFP_H - -/* - * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART1 */ -#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART3 */ -#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* I2c */ -#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) - -/* Fast Ethernet */ -#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) - -/* SPI */ -#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ - -#define MFP_PIN_MAX 117 - -#endif /* __ARMADA100_MFP_H */ diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h deleted file mode 100644 index 9efa1bf..0000000 --- a/arch/arm/include/asm/arch-armada100/spi.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARMADA100_SPI_H_ -#define __ARMADA100_SPI_H_ - -#include <asm/arch/armada100.h> - -#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE -#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) - -/* - * SSP Serial Port Registers - * refer Appendix A.26 - */ -struct ssp_reg { - u32 sscr0; /* SSP Control Register 0 - 0x000 */ - u32 sscr1; /* SSP Control Register 1 - 0x004 */ - u32 sssr; /* SSP Status Register - 0x008 */ - u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ - u32 ssdr; /* SSP Data Register - 0x010 */ - u32 pad1[5]; - u32 ssto; /* SSP Timeout Register - 0x028 */ - u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ - u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ - u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ - u32 sstss; /* SSP Timeslot Status Register - 0x038 */ -}; - -#define DEFAULT_WORD_LEN 8 -#define SSP_FLUSH_NUM 0x2000 -#define RX_THRESH_DEF 8 -#define TX_THRESH_DEF 8 -#define TIMEOUT_DEF 1000 - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity - setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ -#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ - -#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ -#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out - Interrupt enable */ - -#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ -#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF 0x30 /* FRame Format (mask) */ -#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial - Peripheral Interface */ -#define SSCR0_TI (0x1 << 4) /* TI's Synchronous - Serial Protocol (SSP) */ -#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port - Enable */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ - -#endif /* __ARMADA100_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h deleted file mode 100644 index 953dd44..0000000 --- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __UTMI_ARMADA100__ -#define __UTMI_ARMADA100__ - -#define UTMI_PHY_BASE 0xD4206000 - -/* utmi_ctrl - bits */ -#define INPKT_DELAY_SOF (1 << 28) -#define PLL_PWR_UP 2 -#define PHY_PWR_UP 1 - -/* utmi_pll - bits */ -#define PLL_FBDIV_MASK 0x00000FF0 -#define PLL_FBDIV 4 -#define PLL_REFDIV_MASK 0x0000000F -#define PLL_REFDIV 0 -#define PLL_READY 0x800000 -#define VCOCAL_START (1 << 21) - -#define N_DIVIDER 0xEE -#define M_DIVIDER 0x0B - -/* utmi_tx - bits */ -#define CK60_PHSEL 17 -#define PHSEL_VAL 0x4 -#define RCAL_START (1 << 12) - -/* - * USB PHY registers - * Refer Datasheet Appendix A.21 - */ -struct armd1usb_phy_reg { - u32 utmi_rev; /* USB PHY Revision */ - u32 utmi_ctrl; /* USB PHY Control register */ - u32 utmi_pll; /* PLL register */ - u32 utmi_tx; /* Tx register */ - u32 utmi_rx; /* Rx register */ - u32 utmi_ivref; /* IVREF register */ - u32 utmi_tst_g0; /* Test group 0 register */ - u32 utmi_tst_g1; /* Test group 1 register */ - u32 utmi_tst_g2; /* Test group 2 register */ - u32 utmi_tst_g3; /* Test group 3 register */ - u32 utmi_tst_g4; /* Test group 4 register */ - u32 utmi_tst_g5; /* Test group 5 register */ - u32 utmi_reserve; /* Reserve Register */ - u32 utmi_usb_int; /* USB interuppt register */ - u32 utmi_dbg_ctl; /* Debug control register */ - u32 utmi_otg_addon; /* OTG addon register */ -}; - -int utmi_init(void); - -#endif /* __UTMI_ARMADA100__ */ diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig deleted file mode 100644 index 4dd49c4..0000000 --- a/board/Marvell/aspenite/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASPENITE - -config SYS_BOARD - default "aspenite" - -config SYS_VENDOR - default "Marvell" - -config SYS_SOC - default "armada100" - -config SYS_CONFIG_NAME - default "aspenite" - -endif diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS deleted file mode 100644 index a77d30e..0000000 --- a/board/Marvell/aspenite/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ASPENITE BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/aspenite/ -F: include/configs/aspenite.h -F: configs/aspenite_defconfig diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile deleted file mode 100644 index 726d0e4..0000000 --- a/board/Marvell/aspenite/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Contributor: Mahavir Jain mjain@marvell.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := aspenite.o diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c deleted file mode 100644 index 24ee679..0000000 --- a/board/Marvell/aspenite/aspenite.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mvmfp.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mfp.h> -#include <asm/arch/armada100.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u32 mfp_cfg[] = { - /* I2C */ - MFP105_CI2C_SDA, - MFP106_CI2C_SCL, - - /* Enable Console on UART1 */ - MFP107_UART1_RXD, - MFP108_UART1_TXD, - - MFP_EOC /*End of configureation*/ - }; - /* configure MFP's */ - mfp_config(mfp_cfg); - return 0; -} - -int board_init(void) -{ - /* arch number of Board */ - gd->bd->bi_arch_number = MACH_TYPE_ASPENITE; - /* adress of boot parameters */ - gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; - return 0; -} diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig deleted file mode 100644 index d944816..0000000 --- a/board/Marvell/gplugd/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_GPLUGD - -config SYS_BOARD - default "gplugd" - -config SYS_VENDOR - default "Marvell" - -config SYS_SOC - default "armada100" - -config SYS_CONFIG_NAME - default "gplugd" - -endif diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS deleted file mode 100644 index 320bc09..0000000 --- a/board/Marvell/gplugd/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GPLUGD BOARD -M: Ajay Bhargav ajay.bhargav@einfochips.com -S: Maintained -F: board/Marvell/gplugd/ -F: include/configs/gplugd.h -F: configs/gplugd_defconfig diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile deleted file mode 100644 index b384578..0000000 --- a/board/Marvell/gplugd/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2011 -# eInfochips Ltd. <www.einfochips.com> -# Written-by: Ajay Bhargav ajay.bhargav@einfochips.com -# -# Based on Aspenite: -# (C) Copyright 2010 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Contributor: Mahavir Jain mjain@marvell.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := gplugd.o diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c deleted file mode 100644 index 0e8ebcc..0000000 --- a/board/Marvell/gplugd/gplugd.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * Based on Aspenite: - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mvmfp.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mfp.h> -#include <asm/arch/armada100.h> -#include <asm/gpio.h> -#include <miiphy.h> - -#ifdef CONFIG_ARMADA100_FEC -#include <net.h> -#include <netdev.h> -#endif /* CONFIG_ARMADA100_FEC */ - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u32 mfp_cfg[] = { - /* I2C */ - MFP105_CI2C_SDA, - MFP106_CI2C_SCL, - - /* Enable Console on UART3 */ - MFPO8_UART3_TXD, - MFPO9_UART3_RXD, - - /* Ethernet PHY Interface */ - MFP086_ETH_TXCLK, - MFP087_ETH_TXEN, - MFP088_ETH_TXDQ3, - MFP089_ETH_TXDQ2, - MFP090_ETH_TXDQ1, - MFP091_ETH_TXDQ0, - MFP092_ETH_CRS, - MFP093_ETH_COL, - MFP094_ETH_RXCLK, - MFP095_ETH_RXER, - MFP096_ETH_RXDQ3, - MFP097_ETH_RXDQ2, - MFP098_ETH_RXDQ1, - MFP099_ETH_RXDQ0, - MFP100_ETH_MDC, - MFP101_ETH_MDIO, - MFP103_ETH_RXDV, - - /* SSP2 */ - MFP107_SSP2_RXD, - MFP108_SSP2_TXD, - MFP110_SSP2_CS, - MFP111_SSP2_CLK, - - MFP_EOC /*End of configuration*/ - }; - /* configure MFP's */ - mfp_config(mfp_cfg); - return 0; -} - -int board_init(void) -{ - struct armd1apb2_registers *apb2_regs = - (struct armd1apb2_registers *)ARMD1_APBC2_BASE; - - /* arch number of Board */ - gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD; - /* adress of boot parameters */ - gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; - /* Assert PHY_RST# */ - gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW); - udelay(10); - /* Deassert PHY_RST# */ - gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH); - - /* Enable SSP2 clock */ - writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst); - return 0; -} - -#ifdef CONFIG_ARMADA100_FEC -int board_eth_init(bd_t *bis) -{ - struct armd1apmu_registers *apmu_regs = - (struct armd1apmu_registers *)ARMD1_APMU_BASE; - - /* Enable clock of ethernet controller */ - writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); - - return armada100_fec_register(ARMD1_FEC_BASE); -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and initialize PHY chip 88E3015 */ -void reset_phy(void) -{ - u16 phy_adr; - const char *name = "armd-fec0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xff, 0xff, &phy_adr)) { - printf("Err..%s could not read PHY dev address\n", __func__); - return; - } - - /* Set Ethernet LED in TX blink mode */ - miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); - miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); - - /* reset the phy */ - miiphy_reset(name, phy_adr); - debug("88E3015 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ -#endif /* CONFIG_ARMADA100_FEC */ diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig deleted file mode 100644 index 0b341d6..0000000 --- a/configs/aspenite_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_ASPENITE=y diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig deleted file mode 100644 index ec8f45c..0000000 --- a/configs/gplugd_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_GPLUGD=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d78dc93..172386a 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +aspenite arm arm926ejs - - Prafulla Wadaskar prafulla@marvell.com +gplugd arm arm926ejs - - Ajay Bhargav ajay.bhargav@einfochips.com a320evb arm arm920t - - Po-Yu Chuang ratbert@faraday-tech.com cm4008 arm arm920t - - Greg Ungerer greg.ungerer@opengear.com cm41xx arm arm920t - - diff --git a/drivers/net/Makefile b/drivers/net/Makefile index da5e2bc..e7fafa8 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -7,7 +7,6 @@
obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o -obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c deleted file mode 100644 index a8da6b1..0000000 --- a/drivers/net/armada100_fec.c +++ /dev/null @@ -1,726 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <net.h> -#include <malloc.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/types.h> -#include <asm/byteorder.h> -#include <linux/err.h> -#include <linux/mii.h> -#include <asm/io.h> -#include <asm/arch/armada100.h> -#include "armada100_fec.h" - -#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */ - -#ifdef DEBUG -static int eth_dump_regs(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - unsigned int i = 0; - - printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr)); - printf("offset: smi, value: 0x%x\n", readl(®s->smi)); - for (i = 0x400; i <= 0x4e4; i += 4) - printf("offset: 0x%x, value: 0x%x\n", - i, readl(ARMD1_FEC_BASE + i)); - return 0; -} -#endif - -static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond) -{ - u32 timeout = PHY_WAIT_ITERATIONS; - u32 reg_val; - - while (--timeout) { - reg_val = readl(reg); - if (cond && (reg_val & flag)) - break; - else if (!cond && !(reg_val & flag)) - break; - udelay(PHY_WAIT_MICRO_SECONDS); - } - return !timeout; -} - -static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, - u16 *value) -{ - struct eth_device *dev = eth_get_dev_by_name(devname); - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - u32 val; - - if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { - val = readl(®s->phyadr); - *value = val & 0x1f; - return 0; - } - - /* check parameters */ - if (phy_addr > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n", - __func__, phy_addr); - return -EINVAL; - } - if (phy_reg > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n", - __func__, phy_reg); - return -EINVAL; - } - - /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { - printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); - return -1; - } - - writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); - - /* now wait for the data to be valid */ - if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) { - val = readl(®s->smi); - printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", - __func__, val); - return -1; - } - val = readl(®s->smi); - *value = val & 0xffff; - - return 0; -} - -static int smi_reg_write(const char *devname, - u8 phy_addr, u8 phy_reg, u16 value) -{ - struct eth_device *dev = eth_get_dev_by_name(devname); - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - - if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { - clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f); - return 0; - } - - /* check parameters */ - if (phy_addr > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__); - return -EINVAL; - } - if (phy_reg > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__); - return -EINVAL; - } - - /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { - printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); - return -1; - } - - writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff), - ®s->smi); - return 0; -} - -/* - * Abort any transmit and receive operations and put DMA - * in idle state. AT and AR bits are cleared upon entering - * in IDLE state. So poll those bits to verify operation. - */ -static void abortdma(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - int delay; - int maxretries = 40; - u32 tmp; - - while (--maxretries) { - writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd); - udelay(100); - - delay = 10; - while (--delay) { - tmp = readl(®s->sdma_cmd); - if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT))) - break; - udelay(10); - } - if (delay) - break; - } - - if (!maxretries) - printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__); -} - -static inline u32 nibble_swapping_32_bit(u32 x) -{ - return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4); -} - -static inline u32 nibble_swapping_16_bit(u32 x) -{ - return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4); -} - -static inline u32 flip_4_bits(u32 x) -{ - return ((x & 0x01) << 3) | ((x & 0x002) << 1) - | ((x & 0x04) >> 1) | ((x & 0x008) >> 3); -} - -/* - * This function will calculate the hash function of the address. - * depends on the hash mode and hash size. - * Inputs - * mach - the 2 most significant bytes of the MAC address. - * macl - the 4 least significant bytes of the MAC address. - * Outputs - * return the calculated entry. - */ -static u32 hash_function(u32 mach, u32 macl) -{ - u32 hashresult; - u32 addrh; - u32 addrl; - u32 addr0; - u32 addr1; - u32 addr2; - u32 addr3; - u32 addrhswapped; - u32 addrlswapped; - - addrh = nibble_swapping_16_bit(mach); - addrl = nibble_swapping_32_bit(macl); - - addrhswapped = flip_4_bits(addrh & 0xf) - + ((flip_4_bits((addrh >> 4) & 0xf)) << 4) - + ((flip_4_bits((addrh >> 8) & 0xf)) << 8) - + ((flip_4_bits((addrh >> 12) & 0xf)) << 12); - - addrlswapped = flip_4_bits(addrl & 0xf) - + ((flip_4_bits((addrl >> 4) & 0xf)) << 4) - + ((flip_4_bits((addrl >> 8) & 0xf)) << 8) - + ((flip_4_bits((addrl >> 12) & 0xf)) << 12) - + ((flip_4_bits((addrl >> 16) & 0xf)) << 16) - + ((flip_4_bits((addrl >> 20) & 0xf)) << 20) - + ((flip_4_bits((addrl >> 24) & 0xf)) << 24) - + ((flip_4_bits((addrl >> 28) & 0xf)) << 28); - - addrh = addrhswapped; - addrl = addrlswapped; - - addr0 = (addrl >> 2) & 0x03f; - addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2); - addr2 = (addrl >> 15) & 0x1ff; - addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8); - - hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); - hashresult = hashresult & 0x07ff; - return hashresult; -} - -/* - * This function will add an entry to the address table. - * depends on the hash mode and hash size that was initialized. - * Inputs - * mach - the 2 most significant bytes of the MAC address. - * macl - the 4 least significant bytes of the MAC address. - * skip - if 1, skip this address. - * rd - the RD field in the address table. - * Outputs - * address table entry is added. - * 0 if success. - * -ENOSPC if table full - */ -static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach, - u32 macl, u32 rd, u32 skip, int del) -{ - struct addr_table_entry_t *entry, *start; - u32 newhi; - u32 newlo; - u32 i; - - newlo = (((mach >> 4) & 0xf) << 15) - | (((mach >> 0) & 0xf) << 11) - | (((mach >> 12) & 0xf) << 7) - | (((mach >> 8) & 0xf) << 3) - | (((macl >> 20) & 0x1) << 31) - | (((macl >> 16) & 0xf) << 27) - | (((macl >> 28) & 0xf) << 23) - | (((macl >> 24) & 0xf) << 19) - | (skip << HTESKIP) | (rd << HTERDBIT) - | HTEVALID; - - newhi = (((macl >> 4) & 0xf) << 15) - | (((macl >> 0) & 0xf) << 11) - | (((macl >> 12) & 0xf) << 7) - | (((macl >> 8) & 0xf) << 3) - | (((macl >> 21) & 0x7) << 0); - - /* - * Pick the appropriate table, start scanning for free/reusable - * entries at the index obtained by hashing the specified MAC address - */ - start = (struct addr_table_entry_t *)(darmdfec->htpr); - entry = start + hash_function(mach, macl); - for (i = 0; i < HOP_NUMBER; i++) { - if (!(entry->lo & HTEVALID)) { - break; - } else { - /* if same address put in same position */ - if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8)) - && (entry->hi == newhi)) - break; - } - if (entry == start + 0x7ff) - entry = start; - else - entry++; - } - - if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && - (entry->hi != newhi) && del) - return 0; - - if (i == HOP_NUMBER) { - if (!del) { - printf("ARMD100 FEC: (%s) table section is full\n", - __func__); - return -ENOSPC; - } else { - return 0; - } - } - - /* - * Update the selected entry - */ - if (del) { - entry->hi = 0; - entry->lo = 0; - } else { - entry->hi = newhi; - entry->lo = newlo; - } - - return 0; -} - -/* - * Create an addressTable entry from MAC address info - * found in the specifed net_device struct - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - */ -static void update_hash_table_mac_address(struct armdfec_device *darmdfec, - u8 *oaddr, u8 *addr) -{ - u32 mach; - u32 macl; - - /* Delete old entry */ - if (oaddr) { - mach = (oaddr[0] << 8) | oaddr[1]; - macl = (oaddr[2] << 24) | (oaddr[3] << 16) | - (oaddr[4] << 8) | oaddr[5]; - add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE); - } - - /* Add new entry */ - mach = (addr[0] << 8) | addr[1]; - macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; - add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD); -} - -/* Address Table Initialization */ -static void init_hashtable(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE); - writel((u32)darmdfec->htpr, ®s->htpr); -} - -/* - * This detects PHY chip from address 0-31 by reading PHY status - * registers. PHY chip can be connected at any of this address. - */ -static int ethernet_phy_detect(struct eth_device *dev) -{ - u32 val; - u16 tmp, mii_status; - u8 addr; - - for (addr = 0; addr < 32; addr++) { - if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) - /* try next phy */ - continue; - - /* invalid MII status. More validation required here... */ - if (mii_status == 0 || mii_status == 0xffff) - /* try next phy */ - continue; - - if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) - /* try next phy */ - continue; - - val = tmp << 16; - if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) - /* try next phy */ - continue; - - val |= tmp; - - if ((val & 0xfffffff0) != 0) - return addr; - } - return -1; -} - -static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec) -{ - struct rx_desc *p_rx_desc; - int i; - - /* initialize the Rx descriptors ring */ - p_rx_desc = darmdfec->p_rxdesc; - for (i = 0; i < RINGSZ; i++) { - p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; - p_rx_desc->buf_size = PKTSIZE_ALIGN; - p_rx_desc->byte_cnt = 0; - p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN; - if (i == (RINGSZ - 1)) { - p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc; - } else { - p_rx_desc->nxtdesc_p = (struct rx_desc *) - ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE); - p_rx_desc = p_rx_desc->nxtdesc_p; - } - } - darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc; -} - -static int armdfec_init(struct eth_device *dev, bd_t *bd) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - int phy_adr; - u32 temp; - - armdfec_init_rx_desc_ring(darmdfec); - - /* Disable interrupts */ - writel(0, ®s->im); - writel(0, ®s->ic); - /* Write to ICR to clear interrupts. */ - writel(0, ®s->iwc); - - /* - * Abort any transmit and receive operations and put DMA - * in idle state. - */ - abortdma(dev); - - /* Initialize address hash table */ - init_hashtable(dev); - - /* SDMA configuration */ - writel(SDCR_BSZ8 | /* Burst size = 32 bytes */ - SDCR_RIFB | /* Rx interrupt on frame */ - SDCR_BLMT | /* Little endian transmit */ - SDCR_BLMR | /* Little endian receive */ - SDCR_RC_MAX_RETRANS, /* Max retransmit count */ - ®s->sdma_conf); - /* Port Configuration */ - writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */ - - /* Set extended port configuration */ - writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */ - PCXR_DSCP_EN | /* Enable DSCP in IP */ - PCXR_MFL_1536 | /* Set MTU = 1536 */ - PCXR_FLP | /* do not force link pass */ - PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */ - ®s->pconf_ext); - - update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); - - /* Update TX and RX queue descriptor register */ - temp = (u32)®s->txcdp[TXQ]; - writel((u32)darmdfec->p_txdesc, temp); - temp = (u32)®s->rxfdp[RXQ]; - writel((u32)darmdfec->p_rxdesc, temp); - temp = (u32)®s->rxcdp[RXQ]; - writel((u32)darmdfec->p_rxdesc_curr, temp); - - /* Enable Interrupts */ - writel(ALL_INTS, ®s->im); - - /* Enable Ethernet Port */ - setbits_le32(®s->pconf, PCR_EN); - - /* Enable RX DMA engine */ - setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); - -#ifdef DEBUG - eth_dump_regs(dev); -#endif - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) - -#if defined(CONFIG_PHY_BASE_ADR) - miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR); -#else - /* Search phy address from range 0-31 */ - phy_adr = ethernet_phy_detect(dev); - if (phy_adr < 0) { - printf("ARMD100 FEC: PHY not detected at address range 0-31\n"); - return -1; - } else { - debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr); - miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr); - } -#endif - -#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) - /* Wait up to 5s for the link status */ - for (i = 0; i < 5; i++) { - u16 phy_adr; - - miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); - /* Return if we get link up */ - if (miiphy_link(dev->name, phy_adr)) - return 0; - udelay(1000000); - } - - printf("ARMD100 FEC: No link on %s\n", dev->name); - return -1; -#endif -#endif - return 0; -} - -static void armdfec_halt(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - - /* Stop RX DMA */ - clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); - - /* - * Abort any transmit and receive operations and put DMA - * in idle state. - */ - abortdma(dev); - - /* Disable interrupts */ - writel(0, ®s->im); - writel(0, ®s->ic); - writel(0, ®s->iwc); - - /* Disable Port */ - clrbits_le32(®s->pconf, PCR_EN); -} - -static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - struct tx_desc *p_txdesc = darmdfec->p_txdesc; - void *p = (void *)dataptr; - int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS; - u32 cmd_sts, temp; - - /* Copy buffer if it's misaligned */ - if ((u32)dataptr & 0x07) { - if (datasize > PKTSIZE_ALIGN) { - printf("ARMD100 FEC: Non-aligned data too large (%d)\n", - datasize); - return -1; - } - memcpy(darmdfec->p_aligned_txbuf, p, datasize); - p = darmdfec->p_aligned_txbuf; - } - - p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; - p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; - p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; - p_txdesc->cmd_sts |= TX_EN_INT; - p_txdesc->buf_ptr = p; - p_txdesc->byte_cnt = datasize; - - /* Apply send command using high priority TX queue */ - temp = (u32)®s->txcdp[TXQ]; - writel((u32)p_txdesc, temp); - writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd); - - /* - * wait for packet xmit completion - */ - cmd_sts = readl(&p_txdesc->cmd_sts); - while (cmd_sts & BUF_OWNED_BY_DMA) { - /* return fail if error is detected */ - if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == - (TX_ERROR | TX_LAST_DESC)) { - printf("ARMD100 FEC: (%s) in xmit packet\n", __func__); - return -1; - } - cmd_sts = readl(&p_txdesc->cmd_sts); - if (!(retry--)) { - printf("ARMD100 FEC: (%s) xmit packet timeout!\n", - __func__); - return -1; - } - } - - return 0; -} - -static int armdfec_recv(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; - u32 cmd_sts; - u32 timeout = 0; - u32 temp; - - /* wait untill rx packet available or timeout */ - do { - if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) { - timeout++; - } else { - debug("ARMD100 FEC: %s time out...\n", __func__); - return -1; - } - } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA); - - if (p_rxdesc_curr->byte_cnt != 0) { - debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x" - "(cmd_sts= %08x)\n", __func__, - (u32)p_rxdesc_curr->byte_cnt, - (u32)p_rxdesc_curr->buf_ptr, - (u32)p_rxdesc_curr->cmd_sts); - } - - /* - * In case received a packet without first/last bits on - * OR the error summary bit is on, - * the packets needs to be dropeed. - */ - cmd_sts = readl(&p_rxdesc_curr->cmd_sts); - - if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != - (RX_FIRST_DESC | RX_LAST_DESC)) { - printf("ARMD100 FEC: (%s) Dropping packet spread on" - " multiple descriptors\n", __func__); - } else if (cmd_sts & RX_ERROR) { - printf("ARMD100 FEC: (%s) Dropping packet with errors\n", - __func__); - } else { - /* !!! call higher layer processing */ - debug("ARMD100 FEC: (%s) Sending Received packet to" - " upper layer (NetReceive)\n", __func__); - - /* - * let the upper layer handle the packet, subtract offset - * as two dummy bytes are added in received buffer see - * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit. - */ - NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), - (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); - } - /* - * free these descriptors and point next in the ring - */ - p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; - p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; - p_rxdesc_curr->byte_cnt = 0; - - temp = (u32)&darmdfec->p_rxdesc_curr; - writel((u32)p_rxdesc_curr->nxtdesc_p, temp); - - return 0; -} - -int armada100_fec_register(unsigned long base_addr) -{ - struct armdfec_device *darmdfec; - struct eth_device *dev; - - darmdfec = malloc(sizeof(struct armdfec_device)); - if (!darmdfec) - goto error; - - memset(darmdfec, 0, sizeof(struct armdfec_device)); - - darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); - if (!darmdfec->htpr) - goto error1; - - darmdfec->p_rxdesc = memalign(PKTALIGN, - ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); - - if (!darmdfec->p_rxdesc) - goto error1; - - darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1); - if (!darmdfec->p_rxbuf) - goto error1; - - darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); - if (!darmdfec->p_aligned_txbuf) - goto error1; - - darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1); - if (!darmdfec->p_txdesc) - goto error1; - - dev = &darmdfec->dev; - /* Assign ARMADA100 Fast Ethernet Controller Base Address */ - darmdfec->regs = (void *)base_addr; - - /* must be less than sizeof(dev->name) */ - strcpy(dev->name, "armd-fec0"); - - dev->init = armdfec_init; - dev->halt = armdfec_halt; - dev->send = armdfec_send; - dev->recv = armdfec_recv; - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, smi_reg_read, smi_reg_write); -#endif - return 0; - -error1: - free(darmdfec->p_aligned_txbuf); - free(darmdfec->p_rxbuf); - free(darmdfec->p_rxdesc); - free(darmdfec->htpr); -error: - free(darmdfec); - printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__); - return -1; -} diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h deleted file mode 100644 index 5a0a3d9..0000000 --- a/drivers/net/armada100_fec.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARMADA100_FEC_H__ -#define __ARMADA100_FEC_H__ - -#define PORT_NUM 0x0 - -/* RX & TX descriptor command */ -#define BUF_OWNED_BY_DMA (1<<31) - -/* RX descriptor status */ -#define RX_EN_INT (1<<23) -#define RX_FIRST_DESC (1<<17) -#define RX_LAST_DESC (1<<16) -#define RX_ERROR (1<<15) - -/* TX descriptor command */ -#define TX_EN_INT (1<<23) -#define TX_GEN_CRC (1<<22) -#define TX_ZERO_PADDING (1<<18) -#define TX_FIRST_DESC (1<<17) -#define TX_LAST_DESC (1<<16) -#define TX_ERROR (1<<15) - -/* smi register */ -#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */ -#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */ -#define SMI_OP_W (0<<26) /* Write operation */ -#define SMI_OP_R (1<<26) /* Read operation */ - -#define HASH_ADD 0 -#define HASH_DELETE 1 -#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ -#define HOP_NUMBER 12 - -#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ -#define PHY_WAIT_MICRO_SECONDS 10 - -#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ -#define ETH_EXTRA_HEADER (6+6+2+4) - /* dest+src addr+protocol id+crc */ -#define MAX_PKT_SIZE 1536 - - -/* Bit definitions of the SDMA Config Reg */ -#define SDCR_BSZ_OFF 12 -#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF) -#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF) -#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF) -#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF) -#define SDCR_BLMR (1<<6) -#define SDCR_BLMT (1<<7) -#define SDCR_RIFB (1<<9) -#define SDCR_RC_OFF 2 -#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) - -/* SDMA_CMD */ -#define SDMA_CMD_AT (1<<31) -#define SDMA_CMD_TXDL (1<<24) -#define SDMA_CMD_TXDH (1<<23) -#define SDMA_CMD_AR (1<<15) -#define SDMA_CMD_ERD (1<<7) - - -/* Bit definitions of the Port Config Reg */ -#define PCR_HS (1<<12) -#define PCR_EN (1<<7) -#define PCR_PM (1<<0) - -/* Bit definitions of the Port Config Extend Reg */ -#define PCXR_2BSM (1<<28) -#define PCXR_DSCP_EN (1<<21) -#define PCXR_MFL_1518 (0<<14) -#define PCXR_MFL_1536 (1<<14) -#define PCXR_MFL_2048 (2<<14) -#define PCXR_MFL_64K (3<<14) -#define PCXR_FLP (1<<11) -#define PCXR_PRIO_TX_OFF 3 -#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF) - -/* - * * Bit definitions of the Interrupt Cause Reg - * * and Interrupt MASK Reg is the same - * */ -#define ICR_RXBUF (1<<0) -#define ICR_TXBUF_H (1<<2) -#define ICR_TXBUF_L (1<<3) -#define ICR_TXEND_H (1<<6) -#define ICR_TXEND_L (1<<7) -#define ICR_RXERR (1<<8) -#define ICR_TXERR_H (1<<10) -#define ICR_TXERR_L (1<<11) -#define ICR_TX_UDR (1<<13) -#define ICR_MII_CH (1<<28) - -#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ - ICR_TXERR_H | ICR_TXERR_L |\ - ICR_TXEND_H | ICR_TXEND_L |\ - ICR_RXBUF | ICR_RXERR | ICR_MII_CH) - -#define PHY_MASK 0x0000001f - -#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev) -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \ - (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN) - -#define RX_BUF_OFFSET 0x2 -#define RXQ 0x0 /* RX Queue 0 */ -#define TXQ 0x1 /* TX Queue 1 */ - -struct addr_table_entry_t { - u32 lo; - u32 hi; -}; - -/* Bit fields of a Hash Table Entry */ -enum hash_table_entry { - HTEVALID = 1, - HTESKIP = 2, - HTERD = 4, - HTERDBIT = 2 -}; - -struct tx_desc { - u32 cmd_sts; /* Command/status field */ - u16 reserved; - u16 byte_cnt; /* buffer byte count */ - u8 *buf_ptr; /* pointer to buffer for this descriptor */ - struct tx_desc *nextdesc_p; /* Pointer to next descriptor */ -}; - -struct rx_desc { - u32 cmd_sts; /* Descriptor command status */ - u16 byte_cnt; /* Descriptor buffer byte count */ - u16 buf_size; /* Buffer size */ - u8 *buf_ptr; /* Descriptor buffer pointer */ - struct rx_desc *nxtdesc_p; /* Next descriptor pointer */ -}; - -/* - * Armada100 Fast Ethernet controller Registers - * Refer Datasheet Appendix A.22 - */ -struct armdfec_reg { - u32 phyadr; /* PHY Address */ - u32 pad1[3]; - u32 smi; /* SMI */ - u32 pad2[0xFB]; - u32 pconf; /* Port configuration */ - u32 pad3; - u32 pconf_ext; /* Port configuration extend */ - u32 pad4; - u32 pcmd; /* Port Command */ - u32 pad5; - u32 pstatus; /* Port Status */ - u32 pad6; - u32 spar; /* Serial Parameters */ - u32 pad7; - u32 htpr; /* Hash table pointer */ - u32 pad8; - u32 fcsal; /* Flow control source address low */ - u32 pad9; - u32 fcsah; /* Flow control source address high */ - u32 pad10; - u32 sdma_conf; /* SDMA configuration */ - u32 pad11; - u32 sdma_cmd; /* SDMA command */ - u32 pad12; - u32 ic; /* Interrupt cause */ - u32 iwc; /* Interrupt write to clear */ - u32 im; /* Interrupt mask */ - u32 pad13; - u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code - Point to Priority 0 Low */ - u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */ - u32 pad14[3]; - struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor - Pointer */ - u32 pad15[4]; - struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor - Pointer */ - u32 pad16[0x0C]; - struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor - Pointer */ -}; - -struct armdfec_device { - struct eth_device dev; - struct armdfec_reg *regs; - struct tx_desc *p_txdesc; - struct rx_desc *p_rxdesc; - struct rx_desc *p_rxdesc_curr; - u8 *p_rxbuf; - u8 *p_aligned_txbuf; - u8 *htpr; /* hash pointer */ -}; - -#endif /* __ARMADA100_FEC_H__ */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index edbd520..f85e95b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,7 +18,6 @@ endif obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ANDES_SPI) += andes_spi.o -obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c deleted file mode 100644 index 53aaf95..0000000 --- a/drivers/spi/armada100_spi.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Based on SSP driver - * Written-by: Lei Wen leiwen@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <malloc.h> -#include <spi.h> - -#include <asm/io.h> -#include <asm/arch/spi.h> -#include <asm/gpio.h> - -#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave) - -struct armd_spi_slave { - struct spi_slave slave; - struct ssp_reg *spi_reg; - u32 cr0, cr1; - u32 int_cr1; - u32 clear_sr; - const void *tx; - void *rx; - int gpio_cs_inverted; -}; - -static int spi_armd_write(struct armd_spi_slave *pss) -{ - int wait_timeout = SSP_FLUSH_NUM; - while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF)) - ; - if (!wait_timeout) { - debug("%s: timeout error\n", __func__); - return -1; - } - - if (pss->tx != NULL) { - writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr); - ++pss->tx; - } else { - writel(0, &pss->spi_reg->ssdr); - } - return 0; -} - -static int spi_armd_read(struct armd_spi_slave *pss) -{ - int wait_timeout = SSP_FLUSH_NUM; - while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE)) - ; - if (!wait_timeout) { - debug("%s: timeout error\n", __func__); - return -1; - } - - if (pss->rx != NULL) { - *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr); - ++pss->rx; - } else { - readl(&pss->spi_reg->ssdr); - } - return 0; -} - -static int spi_armd_flush(struct armd_spi_slave *pss) -{ - unsigned long limit = SSP_FLUSH_NUM; - - do { - while (readl(&pss->spi_reg->sssr) & SSSR_RNE) - readl(&pss->spi_reg->ssdr); - } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--); - - writel(SSSR_ROR, &pss->spi_reg->sssr); - - return limit; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - gpio_set_value(slave->cs, pss->gpio_cs_inverted); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - gpio_set_value(slave->cs, !pss->gpio_cs_inverted); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct armd_spi_slave *pss; - - pss = spi_alloc_slave(struct armd_spi_slave, bus, cs); - if (!pss) - return NULL; - - pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT); - - pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE; - - pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) | - (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT); - pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); - pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) - | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); - - pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; - pss->clear_sr = SSSR_ROR | SSSR_TINT; - - pss->gpio_cs_inverted = mode & SPI_CS_HIGH; - gpio_set_value(cs, !pss->gpio_cs_inverted); - - return &pss->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - free(pss); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - if (spi_armd_flush(pss) == 0) - return -1; - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - uint bytes = bitlen / 8; - unsigned long limit; - int ret = 0; - - if (bitlen == 0) - goto done; - - /* we can only do 8 bit transfers */ - if (bitlen % 8) { - flags |= SPI_XFER_END; - goto done; - } - - pss->tx = dout; - pss->rx = din; - - if (flags & SPI_XFER_BEGIN) { - spi_cs_activate(slave); - writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1); - writel(TIMEOUT_DEF, &pss->spi_reg->ssto); - writel(pss->cr0, &pss->spi_reg->sscr0); - } - - while (bytes--) { - limit = SSP_FLUSH_NUM; - ret = spi_armd_write(pss); - if (ret) - break; - - while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--) - udelay(1); - - ret = spi_armd_read(pss); - if (ret) - break; - } - - done: - if (flags & SPI_XFER_END) { - /* Stop SSP */ - writel(pss->clear_sr, &pss->spi_reg->sssr); - clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1); - writel(0, &pss->spi_reg->ssto); - spi_cs_deactivate(slave); - } - - return ret; -} diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index c11b551..c1e7953 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -17,7 +17,6 @@ obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
# echi obj-$(CONFIG_USB_EHCI) += ehci-hcd.o -obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o ifdef CONFIG_MPC512X obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c deleted file mode 100644 index 012eb3a..0000000 --- a/drivers/usb/host/ehci-armada100.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * This driver is based on Kirkwood echi driver - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <usb.h> -#include "ehci.h" -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> -#include <asm/arch/utmi-armada100.h> - -/* - * EHCI host controller init - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - if (utmi_init() < 0) - return -1; - - *hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - return 0; -} - -/* - * EHCI host controller stop - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c deleted file mode 100644 index 1e87828..0000000 --- a/drivers/usb/host/utmi-armada100.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <usb.h> -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> -#include <asm/arch/utmi-armada100.h> - -static int utmi_phy_init(void) -{ - struct armd1usb_phy_reg *phy_regs = - (struct armd1usb_phy_reg *)UTMI_PHY_BASE; - int timeout; - - setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); - udelay(1000); - setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); - - clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); - setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); - - setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); - - /* Calibrate pll */ - timeout = 10000; - while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) - ; - if (!timeout) - return -1; - - udelay(200); - setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); - udelay(400); - clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); - - udelay(200); - setbits_le32(&phy_regs->utmi_tx, RCAL_START); - udelay(400); - clrbits_le32(&phy_regs->utmi_tx, RCAL_START); - - timeout = 10000; - while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) - ; - if (!timeout) - return -1; - - return 0; -} - -/* - * Initialize USB host controller's UTMI Physical interface - */ -int utmi_init(void) -{ - struct armd1mpmu_registers *mpmu_regs = - (struct armd1mpmu_registers *)ARMD1_MPMU_BASE; - - struct armd1apmu_registers *apmu_regs = - (struct armd1apmu_registers *)ARMD1_APMU_BASE; - - /* Turn on 26Mhz ref clock for UTMI PLL */ - setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); - - /* USB Clock reset */ - writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc); - writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc); - - /* Initialize UTMI transceiver */ - return utmi_phy_init(); -} diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h deleted file mode 100644 index 727b14a..0000000 --- a/include/configs/aspenite.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ASPENITE_H -#define __CONFIG_ASPENITE_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB" - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */ -#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_MACH_ASPENITE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include <config_cmd_default.h> -#define CONFIG_CMD_I2C -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" -#undef CONFIG_ARCH_MISC_INIT - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#define CONFIG_ENV_SIZE 0x20000 /* 64k */ - -#endif /* __CONFIG_ASPENITE_H */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h deleted file mode 100644 index 404c56a..0000000 --- a/include/configs/gplugd.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com - * - * Based on Aspenite: - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_GPLUGD_H -#define __CONFIG_GPLUGD_H - -/* - * FIXME: fix for error caused due to recent update to mach-types.h - */ -#include <asm/mach-types.h> -#ifdef MACH_TYPE_SHEEVAD -#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this." -#else -#define MACH_TYPE_SHEEVAD 2625 -#endif - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-gplugD" - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */ -#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_MACH_TYPE MACH_TYPE_SHEEVAD /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -#define CONFIG_SYS_TEXT_BASE 0x00f00000 - -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include <config_cmd_default.h> -#define CONFIG_CMD_I2C -#undef CONFIG_CMD_FPGA -#define CONFIG_CMD_USB -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -/* Disable DCACHE */ -#define CONFIG_SYS_DCACHE_OFF - -/* Network configuration */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_ARMADA100_FEC - -/* DHCP Support */ -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 -#endif /* CONFIG_CMD_NET */ - -/* GPIO Support */ -#define CONFIG_MARVELL_GPIO - -/* PHY configuration */ -#define CONFIG_MII -#define CONFIG_CMD_MII -#define CONFIG_RESET_PHY_R -/* 88E3015 register definition */ -#define PHY_LED_PAR_SEL_REG 22 -#define PHY_LED_MAN_REG 25 -#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */ -/* GPIO Configuration for PHY */ -#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ - -/* SPI Support */ -#define CONFIG_ARMADA100_SPI -#define CONFIG_ENV_SPI_CS 110 -#define CONFIG_SYS_SSP_PORT 2 - -/* Flash Support */ -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_ATMEL - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" -#undef CONFIG_ARCH_MISC_INIT - -#ifdef CONFIG_SYS_NS16550_COM1 -#undef CONFIG_SYS_NS16550_COM1 -#endif /* CONFIG_SYS_NS16550_COM1 */ - -#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x4000 -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_OFFSET 0x07C000 - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV - -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ARMADA100 -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#endif /* CONFIG_CMD_USB */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT - -#endif /* __CONFIG_GPLUGD_H */ diff --git a/include/netdev.h b/include/netdev.h index 90140bd..b2bd7c3 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -83,7 +83,6 @@ int sunxi_gmac_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); -int armada100_fec_register(unsigned long base_addr); int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, unsigned long dma_addr); int xilinx_emaclite_of_init(const void *blob);