On Tuesday 09 December 2008, Dirk Eibach wrote:
Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese.
Looks good. Please find some furthe comments below though.
<snip>
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c new file mode 100644 index 0000000..d9982cd --- /dev/null +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -0,0 +1,331 @@ +/*
- (C) Copyright 2008
- Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- Based on board/amcc/yosemite/yosemite.c
- (C) Copyright 2006-2007
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h>
Is this include needed?
+#include <libfdt.h> +#include <fdt_support.h>
And the fdt includes as well?
+DECLARE_GLOBAL_DATA_PTR;
+/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+int board_early_init_f(void) +{
- register uint reg;
- /*
* Setup the external bus controller/chip selects*/- mtdcr(ebccfga, xbcfg);
- reg = mfdcr(ebccfgd);
How about using the mfebc macro:
mfebc(xbcfg, reg);
- mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc()
- /*
* Setup the GPIO pins*/- /* setup Address lines for flash size 64Meg. */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
- /* setup emac */
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
- out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
- /*UART0 and UART1*/
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000);
- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000);
- out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
- out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
- /* disable boot-eeprom WP */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
- out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
- /* external interrupts IRQ0...3 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
- out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
- out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
- /*
* Setup the interrupt controller polarities, triggers, etc.*/- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- /*
* Setup other serial configuration*/- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
- mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
- return 0;
+}
+int misc_init_r(void) +{
- uint pbcr;
- int size_val;
- uint sz;
- /* Re-do sizing to get full correct info */
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
Again, mfebc() seems easier.
- if (gd->bd->bi_flashsize > 0x08000000)
panic("Max. flash banksize is 128 MB!\n");- for (sz = gd->bd->bi_flashsize, size_val = 7;
((sz & 0x08000000) == 0) && (size_val > 0); --size_val)sz <<= 1;- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(ebccfga, pb0cr);
- mtdcr(ebccfgd, pbcr);
mtebc()
<snip>
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 0000000..17ce0a4 --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,203 @@ +/*
- (C) Copyright 2008
- Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- Based on include/configs/yosemite.h
- (C) Copyright 2005-2007
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/*
- gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- High Level Configuration Options
- */
+#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
Indentation look fishy. Please use tab for indention here in all cases.
+/*
- Include common defines/options for all AMCC eval boards
- */
+#include "amcc-common.h"
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+/*
- Base addresses -- Note these are effective addresses where the
- actual resources get mapped (not physical addresses)
- */
+#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1
- 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3
CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/
+#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
+/*
- Initial RAM & stack pointer (placed in SDRAM)
- */
+#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
- CONFIG_SYS_GBL_DATA_SIZE)+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+/*
- Serial Port
- */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE
+/*
- Environment
- Define here the location of the environment variables (FLASH or
EEPROM). + * Note: DENX encourages to use redundant environment in FLASH.
- */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+/*
- FLASH related
- */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */
+/*
- DDR SDRAM
- */
+#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2)
+#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1
+#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000
Indentation look fishy. Perhaps a tab instead of space?
+#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000
+#undef CONFIG_SDRAM_ECC
+/*
- I2C
- */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/
+/*
- Default environment variables
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "ramdisk_addr=fc180000\0" \
- ""
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3
+#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif
+/*
- Commands additional to the ones defined in amcc-common.h
- */
+#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM
+/*
- PCI stuff
- */
+/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
CONFIG_SYS_PCI_MEMBASE */+/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */
+/*
- External Bus Controller (EBC) Setup
- */
+#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
+/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
+#define CONFIG_SYS_EBC_PB1AP 0 +#define CONFIG_SYS_EBC_PB1CR 0 +#define CONFIG_SYS_EBC_PB2AP 0 +#define CONFIG_SYS_EBC_PB2CR 0 +#define CONFIG_SYS_EBC_PB3AP 0 +#define CONFIG_SYS_EBC_PB3CR 0 +#define CONFIG_SYS_EBC_PB4AP 0 +#define CONFIG_SYS_EBC_PB4CR 0
I suggest you remove those defines (CS1...4) completely.
Thanks.
Best regards, Stefan
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