On 16/01/14 17:20, Inha Song wrote:
Hi,
On Thu, 16 Jan 2014 16:50:37 +0900 Minkyu Kang mk7.kang@samsung.com wrote:
On 15/01/14 14:27, Inha Song wrote:
Use setbits/clrbits macro instead of readl/writel function
Signed-off-by: Inha Song ideal.song@samsung.com Signed-off-by: Minkyu Kang mk7.kang@samsung.com Tested-by: Przemyslaw Marczak p.marczak@samsung.com
Changes for v2:
- Coding Style cleanup
- add signed-off-by
arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++---------------------------- 1 file changed, 20 insertions(+), 62 deletions(-)
/* * CLK_SRC_LCD0 @@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_lcd0);
- clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);
0x9? It seems to be 0xf.
I have set the only bit that must be cleared.
In case, I want to set src_lcd0 register to 0x6(b0110). Therefore, do not need to clear a bit of the second and third. (don't care bits)
clrsetbits_le32(addr, 0x9, 0x6) == clrsetbits_le32(addr, 0xf, 0x6) ( reg &= ~b1xx1, reg |= b0110 == reg &= ~b1111, reg |= b0110 )
Do you think any way is better?
No.. 0xF is mask of FIMD0_SEL that is 4 bits. The mask value never be changed.
Thanks, Minkyu Kang.