Hello Marek,
Am 28.02.22 um 15:51 schrieb Marek Vasut:
On 2/28/22 15:13, Wolfgang Grandegger wrote:
The command "ums 0 mmc 0" does not work because the USB port is still in reset. Releasing it in board_usb_init() fixes the problem. This issue has been observed and fixed on the Aries MCVEVP board.
Signed-off-by: Wolfgang Grandegger wg@aries-embedded.de
arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 1 + arch/arm/mach-socfpga/board.c | 8 ++++++++ arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 2 ++ 3 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index ceaec29770..a673837f25 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -12,6 +12,7 @@ aliases { ethernet0 = &gmac0; stmpe-i2c0 = &stmpe1; + udc0 = &usb1; }; chosen { diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7267163222..a2eed73fe9 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -83,6 +83,14 @@ int board_usb_init(int index, enum usb_init_type init) /* Patch the address from OF into the controller pdata. */ socfpga_otg_data.regs_otg = addr; +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 + /* First release reset of the USB port */ + if (addr == SOCFPGA_USB0_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(USB0), 0); + else if (addr == SOCFPGA_USB1_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(USB1), 0); +#endif
Is this really needed at all ?
Yes, it's needed, otherwise "ums 0 mmc 0" does not work. It was working some time ago but commit 430b42f76a4e50ffef7cc2b3c195ff645a438433 did remove the ad-hoc reset code. I realize the issue an on Aries MCVEVP board, but I'm quite sure that it's present on all Cyclone5 boards.
There is drivers/reset/reset-socfpga.c which should handle the reset of the DWC2 USB IP.
See above!
Wolfgang