Make accessor names lowercase to be consistent with coding style. No functional change.
Signed-off-by: Marek Vasut marex@denx.de Cc: Joe Hershberger joe.hershberger@ni.com Cc: Ramon Fried rfried.dev@gmail.com --- drivers/net/dm9000x.c | 214 +++++++++++++++++++++--------------------- 1 file changed, 107 insertions(+), 107 deletions(-)
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 4f062e99d9b..93699135f75 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -104,24 +104,24 @@ static board_info_t dm9000_info; static int dm9000_probe(void); static u16 dm9000_phy_read(int); static void dm9000_phy_write(int, u16); -static u8 DM9000_ior(int); -static void DM9000_iow(int reg, u8 value); +static u8 dm9000_ior(int); +static void dm9000_iow(int reg, u8 value);
/* DM9000 network board routine ---------------------------- */ #ifndef CONFIG_DM9000_BYTE_SWAPPED -#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r)) -#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r)) -#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r)) -#define DM9000_inb(r) readb((volatile u8 *)(r)) -#define DM9000_inw(r) readw((volatile u16 *)(r)) -#define DM9000_inl(r) readl((volatile u32 *)(r)) +#define dm9000_outb(d,r) writeb(d, (volatile u8 *)(r)) +#define dm9000_outw(d,r) writew(d, (volatile u16 *)(r)) +#define dm9000_outl(d,r) writel(d, (volatile u32 *)(r)) +#define dm9000_inb(r) readb((volatile u8 *)(r)) +#define dm9000_inw(r) readw((volatile u16 *)(r)) +#define dm9000_inl(r) readl((volatile u32 *)(r)) #else -#define DM9000_outb(d, r) __raw_writeb(d, r) -#define DM9000_outw(d, r) __raw_writew(d, r) -#define DM9000_outl(d, r) __raw_writel(d, r) -#define DM9000_inb(r) __raw_readb(r) -#define DM9000_inw(r) __raw_readw(r) -#define DM9000_inl(r) __raw_readl(r) +#define dm9000_outb(d, r) __raw_writeb(d, r) +#define dm9000_outw(d, r) __raw_writew(d, r) +#define dm9000_outl(d, r) __raw_writel(d, r) +#define dm9000_inb(r) __raw_readb(r) +#define dm9000_inw(r) __raw_readw(r) +#define dm9000_inl(r) __raw_readl(r) #endif
#ifdef CONFIG_DM9000_DEBUG @@ -129,14 +129,14 @@ static void dump_regs(void) { DM9000_DBG("\n"); - DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); - DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); - DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); - DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); - DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); - DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); - DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); - DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); + DM9000_DBG("NCR (0x00): %02x\n", dm9000_ior(0)); + DM9000_DBG("NSR (0x01): %02x\n", dm9000_ior(1)); + DM9000_DBG("TCR (0x02): %02x\n", dm9000_ior(2)); + DM9000_DBG("TSRI (0x03): %02x\n", dm9000_ior(3)); + DM9000_DBG("TSRII (0x04): %02x\n", dm9000_ior(4)); + DM9000_DBG("RCR (0x05): %02x\n", dm9000_ior(5)); + DM9000_DBG("RSR (0x06): %02x\n", dm9000_ior(6)); + DM9000_DBG("ISR (0xFE): %02x\n", dm9000_ior(DM9000_ISR)); DM9000_DBG("\n"); } #endif @@ -145,7 +145,7 @@ static void dm9000_outblk_8bit(volatile void *data_ptr, int count) { int i; for (i = 0; i < count; i++) - DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); + dm9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); }
static void dm9000_outblk_16bit(volatile void *data_ptr, int count) @@ -154,7 +154,7 @@ static void dm9000_outblk_16bit(volatile void *data_ptr, int count) u32 tmplen = (count + 1) / 2;
for (i = 0; i < tmplen; i++) - DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); + dm9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); } static void dm9000_outblk_32bit(volatile void *data_ptr, int count) { @@ -162,14 +162,14 @@ static void dm9000_outblk_32bit(volatile void *data_ptr, int count) u32 tmplen = (count + 3) / 4;
for (i = 0; i < tmplen; i++) - DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); + dm9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); }
static void dm9000_inblk_8bit(void *data_ptr, int count) { int i; for (i = 0; i < count; i++) - ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); + ((u8 *) data_ptr)[i] = dm9000_inb(DM9000_DATA); }
static void dm9000_inblk_16bit(void *data_ptr, int count) @@ -178,7 +178,7 @@ static void dm9000_inblk_16bit(void *data_ptr, int count) u32 tmplen = (count + 1) / 2;
for (i = 0; i < tmplen; i++) - ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); + ((u16 *) data_ptr)[i] = dm9000_inw(DM9000_DATA); } static void dm9000_inblk_32bit(void *data_ptr, int count) { @@ -186,38 +186,38 @@ static void dm9000_inblk_32bit(void *data_ptr, int count) u32 tmplen = (count + 3) / 4;
for (i = 0; i < tmplen; i++) - ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); + ((u32 *) data_ptr)[i] = dm9000_inl(DM9000_DATA); }
static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) { u32 tmpdata;
- DM9000_outb(DM9000_MRCMD, DM9000_IO); + dm9000_outb(DM9000_MRCMD, DM9000_IO);
- tmpdata = DM9000_inl(DM9000_DATA); + tmpdata = dm9000_inl(DM9000_DATA); *RxStatus = __le16_to_cpu(tmpdata); *RxLen = __le16_to_cpu(tmpdata >> 16); }
static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) { - DM9000_outb(DM9000_MRCMD, DM9000_IO); + dm9000_outb(DM9000_MRCMD, DM9000_IO);
- *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA)); - *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA)); + *RxStatus = __le16_to_cpu(dm9000_inw(DM9000_DATA)); + *RxLen = __le16_to_cpu(dm9000_inw(DM9000_DATA)); }
static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) { - DM9000_outb(DM9000_MRCMD, DM9000_IO); + dm9000_outb(DM9000_MRCMD, DM9000_IO);
*RxStatus = - __le16_to_cpu(DM9000_inb(DM9000_DATA) + - (DM9000_inb(DM9000_DATA) << 8)); + __le16_to_cpu(dm9000_inb(DM9000_DATA) + + (dm9000_inb(DM9000_DATA) << 8)); *RxLen = - __le16_to_cpu(DM9000_inb(DM9000_DATA) + - (DM9000_inb(DM9000_DATA) << 8)); + __le16_to_cpu(dm9000_inb(DM9000_DATA) + + (dm9000_inb(DM9000_DATA) << 8)); }
/* @@ -227,10 +227,10 @@ int dm9000_probe(void) { u32 id_val; - id_val = DM9000_ior(DM9000_VIDL); - id_val |= DM9000_ior(DM9000_VIDH) << 8; - id_val |= DM9000_ior(DM9000_PIDL) << 16; - id_val |= DM9000_ior(DM9000_PIDH) << 24; + id_val = dm9000_ior(DM9000_VIDL); + id_val |= dm9000_ior(DM9000_VIDH) << 8; + id_val |= dm9000_ior(DM9000_PIDL) << 16; + id_val |= dm9000_ior(DM9000_PIDH) << 24; if (id_val == DM9000_ID) { printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, id_val); @@ -252,28 +252,28 @@ dm9000_reset(void) see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
/* DEBUG: Make all GPIO0 outputs, all others inputs */ - DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); + dm9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ - DM9000_iow(DM9000_GPR, 0); + dm9000_iow(DM9000_GPR, 0); /* Step 2: Software reset */ - DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); + dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
do { DM9000_DBG("resetting the DM9000, 1st reset\n"); udelay(25); /* Wait at least 20 us */ - } while (DM9000_ior(DM9000_NCR) & 1); + } while (dm9000_ior(DM9000_NCR) & 1);
- DM9000_iow(DM9000_NCR, 0); - DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ + dm9000_iow(DM9000_NCR, 0); + dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
do { DM9000_DBG("resetting the DM9000, 2nd reset\n"); udelay(25); /* Wait at least 20 us */ - } while (DM9000_ior(DM9000_NCR) & 1); + } while (dm9000_ior(DM9000_NCR) & 1);
/* Check whether the ethernet controller is present */ - if ((DM9000_ior(DM9000_PIDL) != 0x0) || - (DM9000_ior(DM9000_PIDH) != 0x90)) + if ((dm9000_ior(DM9000_PIDL) != 0x0) || + (dm9000_ior(DM9000_PIDH) != 0x90)) printf("ERROR: resetting DM9000 -> not responding\n"); }
@@ -294,7 +294,7 @@ static int dm9000_init(struct eth_device *dev, struct bd_info *bd) return -1;
/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ - io_mode = DM9000_ior(DM9000_ISR) >> 6; + io_mode = dm9000_ior(DM9000_ISR) >> 6;
switch (io_mode) { case 0x0: /* 16-bit mode */ @@ -325,21 +325,21 @@ static int dm9000_init(struct eth_device *dev, struct bd_info *bd) }
/* Program operating register, only internal phy supported */ - DM9000_iow(DM9000_NCR, 0x0); + dm9000_iow(DM9000_NCR, 0x0); /* TX Polling clear */ - DM9000_iow(DM9000_TCR, 0); + dm9000_iow(DM9000_TCR, 0); /* Less 3Kb, 200us */ - DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); + dm9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); /* Flow Control : High/Low Water */ - DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); + dm9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* SH FIXME: This looks strange! Flow Control */ - DM9000_iow(DM9000_FCR, 0x0); + dm9000_iow(DM9000_FCR, 0x0); /* Special Mode */ - DM9000_iow(DM9000_SMCR, 0); + dm9000_iow(DM9000_SMCR, 0); /* clear TX status */ - DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); + dm9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* Clear interrupt status */ - DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); + dm9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
printf("MAC: %pM\n", dev->enetaddr); if (!is_valid_ethaddr(dev->enetaddr)) { @@ -348,20 +348,20 @@ static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
/* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) - DM9000_iow(oft, dev->enetaddr[i]); + dm9000_iow(oft, dev->enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) - DM9000_iow(oft, 0xff); + dm9000_iow(oft, 0xff);
/* read back mac, just to be sure */ for (i = 0, oft = 0x10; i < 6; i++, oft++) - DM9000_DBG("%02x:", DM9000_ior(oft)); + DM9000_DBG("%02x:", dm9000_ior(oft)); DM9000_DBG("\n");
/* Activate DM9000 */ /* RX enable */ - DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); + dm9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* Enable TX/RX interrupt mask */ - DM9000_iow(DM9000_IMR, IMR_PAR); + dm9000_iow(DM9000_IMR, IMR_PAR);
i = 0; while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */ @@ -408,31 +408,31 @@ static int dm9000_send(struct eth_device *netdev, void *packet, int length)
DM9000_DMP_PACKET(__func__ , packet, length);
- DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
/* Move data to DM9000 TX RAM */ - DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ + dm9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
/* push the data to the TX-fifo */ (db->outblk)(packet, length);
/* Set TX length to DM9000 */ - DM9000_iow(DM9000_TXPLL, length & 0xff); - DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); + dm9000_iow(DM9000_TXPLL, length & 0xff); + dm9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
/* Issue TX polling command */ - DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + dm9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
/* wait for end of transmission */ tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; - while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || - !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { + while ( !(dm9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || + !(dm9000_ior(DM9000_ISR) & IMR_PTM) ) { if (get_timer(0) >= tmo) { printf("transmission timeout\n"); break; } } - DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
DM9000_DBG("transmit done\n\n"); return 0; @@ -448,9 +448,9 @@ static void dm9000_halt(struct eth_device *netdev)
/* RESET devie */ dm9000_phy_write(0, 0x8000); /* PHY RESET */ - DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ - DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ - DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ + dm9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ + dm9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ + dm9000_iow(DM9000_RCR, 0x00); /* Disable RX */ }
/* @@ -465,23 +465,23 @@ static int dm9000_rx(struct eth_device *netdev)
/* Check packet ready or not, we must check the ISR status first for DM9000A */ - if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ + if (!(dm9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ return 0;
- DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ + dm9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
/* There is _at least_ 1 package in the fifo, read them all */ for (;;) { - DM9000_ior(DM9000_MRCMDX); /* Dummy read */ + dm9000_ior(DM9000_MRCMDX); /* Dummy read */
/* Get most updated data, only look at bits 0:1, See application notes DM9000 */ - rxbyte = DM9000_inb(DM9000_DATA) & 0x03; + rxbyte = dm9000_inb(DM9000_DATA) & 0x03;
/* Status check: this byte must be 0 or 1 */ if (rxbyte > DM9000_PKT_RDY) { - DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ - DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + dm9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + dm9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ printf("DM9000 error: status check fail: 0x%x\n", rxbyte); return 0; @@ -532,22 +532,22 @@ static int dm9000_rx(struct eth_device *netdev) #if !defined(CONFIG_DM9000_NO_SROM) void dm9000_read_srom_word(int offset, u8 *to) { - DM9000_iow(DM9000_EPAR, offset); - DM9000_iow(DM9000_EPCR, 0x4); + dm9000_iow(DM9000_EPAR, offset); + dm9000_iow(DM9000_EPCR, 0x4); udelay(8000); - DM9000_iow(DM9000_EPCR, 0x0); - to[0] = DM9000_ior(DM9000_EPDRL); - to[1] = DM9000_ior(DM9000_EPDRH); + dm9000_iow(DM9000_EPCR, 0x0); + to[0] = dm9000_ior(DM9000_EPDRL); + to[1] = dm9000_ior(DM9000_EPDRH); }
void dm9000_write_srom_word(int offset, u16 val) { - DM9000_iow(DM9000_EPAR, offset); - DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); - DM9000_iow(DM9000_EPDRL, (val & 0xff)); - DM9000_iow(DM9000_EPCR, 0x12); + dm9000_iow(DM9000_EPAR, offset); + dm9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + dm9000_iow(DM9000_EPDRL, (val & 0xff)); + dm9000_iow(DM9000_EPCR, 0x12); udelay(8000); - DM9000_iow(DM9000_EPCR, 0); + dm9000_iow(DM9000_EPCR, 0); } #endif
@@ -564,20 +564,20 @@ static void dm9000_get_enetaddr(struct eth_device *dev) Read a byte from I/O port */ static u8 -DM9000_ior(int reg) +dm9000_ior(int reg) { - DM9000_outb(reg, DM9000_IO); - return DM9000_inb(DM9000_DATA); + dm9000_outb(reg, DM9000_IO); + return dm9000_inb(DM9000_DATA); }
/* Write a byte to I/O port */ static void -DM9000_iow(int reg, u8 value) +dm9000_iow(int reg, u8 value) { - DM9000_outb(reg, DM9000_IO); - DM9000_outb(value, DM9000_DATA); + dm9000_outb(reg, DM9000_IO); + dm9000_outb(value, DM9000_DATA); }
/* @@ -589,11 +589,11 @@ dm9000_phy_read(int reg) u16 val;
/* Fill the phyxcer register into REG_0C */ - DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); - DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ + dm9000_iow(DM9000_EPAR, DM9000_PHY | reg); + dm9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ udelay(100); /* Wait read complete */ - DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ - val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); + dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + val = (dm9000_ior(DM9000_EPDRH) << 8) | dm9000_ior(DM9000_EPDRL);
/* The read data keeps on REG_0D & REG_0E */ DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val); @@ -608,14 +608,14 @@ dm9000_phy_write(int reg, u16 value) {
/* Fill the phyxcer register into REG_0C */ - DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + dm9000_iow(DM9000_EPAR, DM9000_PHY | reg);
/* Fill the written data into REG_0D & REG_0E */ - DM9000_iow(DM9000_EPDRL, (value & 0xff)); - DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); - DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ + dm9000_iow(DM9000_EPDRL, (value & 0xff)); + dm9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); + dm9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ udelay(500); /* Wait write complete */ - DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value); }