On 6/2/21 3:08 PM, Ramon Fried wrote:
On Tue, Jun 1, 2021 at 12:35 AM Heinrich Schuchardt xypron.glpk@gmx.de wrote:
Dear all,
network is broken in U-Boot on orangepi_pc_defconfig:
U-Boot 2021.07-rc3-00059-gd8729a114e (May 31 2021 - 21:26:56 +0000) Allwinner Technology eth0: ethernet@1c30000 => dhcp sun8i_emac_eth_start: Timeout
Best regards
Heinrich
Hi Heinrich, I don't have OrangePi. can you bisect and tell me when it broke ? Thanks. Ramon.
Git bisect points to:
commit 4f0278dac56a658ef1e0967fec0bb95372a875bd Author: Andre Przywara andre.przywara@arm.com Date: Mon Jul 6 01:40:45 2020 +0100
net: sun8i-emac: Lower MDIO frequency
Reverting the patch solves the problem for the OrangePi PC.
According to the commit message the change was only needed for needed for external PHYs. Can't we let the change depend on priv->use_internal_phy?
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5a1b38bf80..d7553fe163 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) * The EMAC clock is either 200 or 300 MHz, so we need a divider * of 128 to get the MDIO frequency below the required 2.5 MHz. */ - mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT; + if (!priv->use_internal_phy) + mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << + MDIO_CMD_MII_CLK_CSR_SHIFT;
mii_cmd |= MDIO_CMD_MII_BUSY;
@@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, * The EMAC clock is either 200 or 300 MHz, so we need a divider * of 128 to get the MDIO frequency below the required 2.5 MHz. */ - mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT; + if (!priv->use_internal_phy) + mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << + MDIO_CMD_MII_CLK_CSR_SHIFT;
mii_cmd |= MDIO_CMD_MII_WRITE; mii_cmd |= MDIO_CMD_MII_BUSY;
Best regards
Heinrich
I would assume the problem hits all H3 boards.
Best regards
Heinrich