On 9/14/2010 12:46 PM, Stefan Roese wrote: Hello Stefan,
On Tuesday 14 September 2010 07:22:10 Vipin Kumar wrote:
This is about a generic problem which may also be faced by other developers. Our SoC has a masked bootrom area which copies an image from NOR/NAND memories to an internal embedded SRAM. The size of this SRAM is only 8K. This binary initializes the DDR for larger binaries (u-boot/OS) to be placed in RAM and executed from there.
I wanted to know if there is a generic way to create two binaries from the u-boot source both compiled for different address ranges. The first initializes the RAM (may be something else as well) and the second is the u-boot binary responsible for loading OS etc.
Take a look at the NAND_SPL infrastructure (nand_spl/*). It was created for platforms booting from NAND with tight restrictions (e.g. 4k image size for inital setup, mostly DDR). General idea here is that 2 images are created:
a) Very small SPL (secondary program loader) image with only basic setup, like DDR and NAND b) RAM based U-Boot image
Both images are combined in the build process creating a single image that can be flashed into NAND.
doc/README.nand-boot-ppc440 might be interesting to get some more infos about this, some of it PPC4xx specific though.
Yes, got it. The only point is that this is meant to boot from NAND, ONENAND devices(As the name suggests). Can there be a generic interface independent of a particular device.
Offcourse I agree that execute in place would work for NOR devices and we wont need this kinda solution but still a generic solution for both types of devices is preferable
Regards Vipin