I am in the process of bringing up a custom SBC with an MPC8540. I am using the BDI2000 to debug. When I trace through the code, the system halts in _start_e500 in start.S where it invalidates MMU L1/L2. I have a Rev 1 processor, and the errata is included at the top of _start_e500. It seems to fail at isync. I have included some screen captures from the BDI2000 and the source.
BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff14c Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff150 Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 BDI>ti - Core status is 0x0041 *** Core is stopped, no restart possible # PPC: timeout while waiting for halt BDI> Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : COP freeze Current PC : 0x00000000 Current CR : 0x00000000 Current MSR : 0x00000000 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 # Step timeout detected BDI>
start.S /* * Invalidate MMU L1/L2 * * Note: There is a fixup earlier for Errata CPU4 on * Rev 1 parts that must precede this MMU invalidation. */ li r2, 0x001e mtspr MMUCSR0, r2 isync
start.S objdump: 140: 38 20 20 00 li r1,8192 144: 7c 3f 63 a6 mtspr 415,r1 148: 38 40 00 1e li r2,30 14c: 7c 54 fb a6 mtiac1 r2 150: 4c 00 01 2c isync 154: 38 60 00 04 li r3,4
Could the initializationt that the BDI does be interfering here? Any help would be greatly appreciated.
Thanks, Jeff Stevens
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