Attached a patch that adds support for the 16-bit wide bus of System ACE CF besides the existing support for the 8-bit wide bus.
The patch also #ifdef's accesses to the System ACE CF configuration controller. In combination with a Xilinx FPGA the reset sequence resulted in the reconfiguration of the FPGA, an undesired result. The patch excludes that reset sequence if U-Boot is run on an ML300 board.
The patch also fixes two typos.
- Peter
* Add System ACE CF support for 16-bit bus width Avoid resetting the configuration controller if System ACE CF is accessed from an FPGA (e.g. on the ML300 board). Patch by Peter Ryser, 24 Jan 2006
diff --git a/common/cmd_ace.c b/common/cmd_ace.c index b6d6105..9914415 100644 --- a/common/cmd_ace.c +++ b/common/cmd_ace.c @@ -22,8 +22,9 @@ /* * The Xilinx SystemACE chip support is activated by defining * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE - * to set the base address of the device. This code currently - * assumes that the chip is connected via a byte-wide bus. + * to set the base address of the device. CFG_SYSTEMACE_WIDTH + * selects the bus width the chip is connected with. Valid + * settings are 8 or 16. * * The CONFIG_SYSTEMACE also adds to fat support the device class * "ace" that allows the user to execute "fatls ace 0" and the @@ -138,6 +139,11 @@ block_dev_desc_t * systemace_get_dev(in systemace_dev.removable = 1; systemace_dev.block_read = systemace_read;
+ if(CFG_SYSTEMACE_WIDTH == 8) + ace_writew(0, 0); + else + ace_writew(1, 0); + init_part(&systemace_dev);
} @@ -226,10 +232,12 @@ static unsigned long systemace_read(int /* Write sector count | ReadMemCardData. */ ace_writew((trans&0xff) | 0x0300, 0x14);
- /* Reset the configruation controller */ +#if !defined(CONFIG_XILINX_ML300) + /* Reset the configuration controller */ val = ace_readw(0x18); val|=0x0080; ace_writew(val, 0x18); +#endif
retry = trans * 16; while (retry > 0) { @@ -250,10 +258,12 @@ static unsigned long systemace_read(int retry -= 1; }
- /* Clear the configruation controller reset */ +#if !defined(CONFIG_XILINX_ML300) + /* Clear the configuration controller reset */ val = ace_readw(0x18); val&=~0x0080; ace_writew(val, 0x18); +#endif
/* Count the blocks we transfer this time. */ start += trans;