This series adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V.
Some existing RISC-V codes have been changed to make it easily to support new targets. Some spotted coding style issues are fixed.
This series is available at u-boot-x86/riscv-working for testing.
Resend v2 to rebase on top of v2018.09 release with Tom's tree on github, as the git.denx.de is still out of sync ...
Changes in v2: - Change Linux kernel entry parameters' type to support 32/64 bit - new patch to remove CSR read/write defines in encoding.h - new patch to pass mhartid CSR value to kernel - new patch to move do_reset() to a common place
Bin Meng (15): riscv: kconfig: Normalize architecture name spelling riscv: Remove setup.h riscv: bootm: Correct the 1st kernel argument to hart id riscv: Remove mach type riscv: Move the linker script to the CPU root directory riscv: Fix coding style issues in the linker script riscv: Explicitly pass -march and -mabi to the compiler riscv: Add a helper routine to print CPU information riscv: Remove CSR read/write defines in encoding.h riscv: bootm: Pass mhartid CSR value to kernel riscv: Make start.S available for all targets riscv: ae350: Clean up mixed tabs and spaces in the dts riscv: kconfig: Select DM and OF_CONTROL riscv: Add QEMU virt board support riscv: Move do_reset() to a common place
arch/Kconfig | 5 +- arch/riscv/Kconfig | 10 +- arch/riscv/Makefile | 3 +- arch/riscv/config.mk | 9 +- arch/riscv/cpu/Makefile | 7 ++ arch/riscv/cpu/ax25/Makefile | 2 - arch/riscv/cpu/ax25/cpu.c | 9 -- arch/riscv/cpu/cpu.c | 49 ++++++++ arch/riscv/cpu/qemu/Makefile | 6 + arch/riscv/cpu/qemu/cpu.c | 21 ++++ arch/riscv/cpu/qemu/dram.c | 17 +++ arch/riscv/cpu/{ax25 => }/start.S | 0 arch/riscv/cpu/{ax25 => }/u-boot.lds | 60 +++++----- arch/riscv/dts/ae350.dts | 177 +++++++++++++++-------------- arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/csr.h | 124 ++++++++++++++++++++ arch/riscv/include/asm/encoding.h | 50 +------- arch/riscv/include/asm/mach-types.h | 29 ----- arch/riscv/include/asm/setup.h | 194 -------------------------------- arch/riscv/include/asm/u-boot.h | 1 - arch/riscv/lib/Makefile | 1 + arch/riscv/lib/bootm.c | 20 +--- arch/riscv/lib/reset.c | 14 +++ board/AndesTech/ax25-ae350/ax25-ae350.c | 2 - board/emulation/qemu-riscv/Kconfig | 21 ++++ board/emulation/qemu-riscv/MAINTAINERS | 7 ++ board/emulation/qemu-riscv/Makefile | 5 + board/emulation/qemu-riscv/qemu-riscv.c | 23 ++++ cmd/bdinfo.c | 1 - configs/ax25-ae350_defconfig | 2 - configs/qemu-riscv32_defconfig | 10 ++ configs/qemu-riscv64_defconfig | 11 ++ doc/README.qemu-riscv | 46 ++++++++ include/configs/qemu-riscv.h | 21 ++++ 34 files changed, 532 insertions(+), 438 deletions(-) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/cpu/qemu/Makefile create mode 100644 arch/riscv/cpu/qemu/cpu.c create mode 100644 arch/riscv/cpu/qemu/dram.c rename arch/riscv/cpu/{ax25 => }/start.S (100%) rename arch/riscv/cpu/{ax25 => }/u-boot.lds (54%) delete mode 100644 arch/riscv/include/asm/bootm.h create mode 100644 arch/riscv/include/asm/csr.h delete mode 100644 arch/riscv/include/asm/mach-types.h delete mode 100644 arch/riscv/include/asm/setup.h create mode 100644 arch/riscv/lib/reset.c create mode 100644 board/emulation/qemu-riscv/Kconfig create mode 100644 board/emulation/qemu-riscv/MAINTAINERS create mode 100644 board/emulation/qemu-riscv/Makefile create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c create mode 100644 configs/qemu-riscv32_defconfig create mode 100644 configs/qemu-riscv64_defconfig create mode 100644 doc/README.qemu-riscv create mode 100644 include/configs/qemu-riscv.h