Use standard pinconf drive-strength values from Linux DT bindings rather than ones based on custom u-boot header. These changes are in direction to make u-boot DTs for Qcom SoCs to be compatible with standard Linux DT bindings.
Also, add support for pinconf bias-pull-up.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/dts/dragonboard410c.dts | 3 +-- arch/arm/dts/dragonboard820c.dts | 3 +-- arch/arm/dts/qcom-ipq4019.dtsi | 1 - arch/arm/dts/qcs404-evb.dts | 1 - arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 8 ++++++- .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 ------------------- 6 files changed, 9 insertions(+), 29 deletions(-) delete mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index 59cf45eb17..9230dd3fd9 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -9,7 +9,6 @@
#include "skeleton64.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ { model = "Qualcomm Technologies, Inc. Dragonboard 410c"; @@ -71,7 +70,7 @@ blsp1_uart: uart { function = "blsp1_uart"; pins = "GPIO_4", "GPIO_5"; - drive-strength = <DRIVE_STRENGTH_8MA>; + drive-strength = <8>; bias-disable; }; }; diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index aaca681d2e..ad201d4874 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -8,7 +8,6 @@ /dts-v1/;
#include "skeleton64.dtsi" -#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ { model = "Qualcomm Technologies, Inc. DB820c"; @@ -71,7 +70,7 @@ blsp8_uart: uart { function = "blsp_uart8"; pins = "GPIO_4", "GPIO_5"; - drive-strength = <DRIVE_STRENGTH_8MA>; + drive-strength = <8>; bias-disable; }; }; diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 181732d262..6edc69da67 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -9,7 +9,6 @@
#include "skeleton.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/pinctrl-snapdragon.h> #include <dt-bindings/clock/qcom,ipq4019-gcc.h> #include <dt-bindings/reset/qcom,ipq4019-reset.h>
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index c8bcf9f71d..cc70afa4c8 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -9,7 +9,6 @@
#include "skeleton64.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/pinctrl-snapdragon.h> #include <dt-bindings/clock/qcom,gcc-qcs404.h>
/ { diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index ab884ab6bf..826dc51486 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -28,8 +28,9 @@ struct msm_pinctrl_priv { #define TLMM_GPIO_DISABLE BIT(9)
static const struct pinconf_param msm_conf_params[] = { - { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, };
static int msm_get_functions_count(struct udevice *dev) @@ -89,6 +90,7 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: + argument = (argument / 2) - 1; clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), TLMM_DRV_STRENGTH_MASK, argument << 6); break; @@ -96,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), TLMM_GPIO_PULL_MASK); break; + case PIN_CONFIG_BIAS_PULL_UP: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK, argument); + break; default: return 0; } diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h deleted file mode 100644 index 615affb6f2..0000000000 --- a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * This header provides constants for Qualcomm Snapdragon pinctrl bindings. - * - * (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com - * - */ - -#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H -#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H - -/* GPIO Drive Strength */ -#define DRIVE_STRENGTH_2MA 0 -#define DRIVE_STRENGTH_4MA 1 -#define DRIVE_STRENGTH_6MA 2 -#define DRIVE_STRENGTH_8MA 3 -#define DRIVE_STRENGTH_10MA 4 -#define DRIVE_STRENGTH_12MA 5 -#define DRIVE_STRENGTH_14MA 6 -#define DRIVE_STRENGTH_16MA 7 - -#endif