Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Prabhakar Lad prabhakar.csengg@gmail.com --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 ++- arch/arm/include/asm/arch-davinci/hardware.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 6cb857a..41201d0 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -194,7 +194,8 @@ int set_cpu_clk_info(void) #ifdef CONFIG_SOC_DA8XX gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); #else
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 0fce940..7f3dcc2 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -459,10 +459,12 @@ enum davinci_clk_ids { DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,