From: Chao Fu B44548@freescale.com
This patch enable the DSPI moudle on VF610 platform with following udpate: Add get_dspi_clk() function and enable DPSI clock gate. Add DSPI iomux definition and set the iomux for DSPI.
Signed-off-by: Chao Fu b44548@freescale.com --- Change in v2: Separated vf610-twr update into patch 3/4.
arch/arm/cpu/armv7/vf610/generic.c | 7 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 1 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 8 ++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 5 files changed, 19 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index a26d63e..266343e 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -196,6 +196,11 @@ static u32 get_i2c_clk(void) return get_ipg_clk(); }
+static u32 get_dspi_clk(void) +{ + return get_ipg_clk(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -213,6 +218,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_fec_clk(); case MXC_I2C_CLK: return get_i2c_clk(); + case MXC_DSPI_CLK: + return get_dspi_clk(); default: break; } diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 535adad..e5a5c6d 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -17,6 +17,7 @@ enum mxc_clock { MXC_ESDHC_CLK, MXC_FEC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, };
void enable_ocotp_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda..a03c627 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -165,6 +165,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 4a39eb0..2942ebd 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -19,6 +19,10 @@ #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm #define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE | PAD_CTL_DSE_25ohm | \ + PAD_CTL_SPEED_MED) +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE | PAD_CTL_DSE_25ohm | \ + PAD_CTL_SPEED_MED)
enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -41,6 +45,10 @@ enum { VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTB19__DSPI0_CS0 = IOMUX_PAD(0x00a4, 0x00a4, 1, __NA_, 0, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTB20__DSPI0_SIN = IOMUX_PAD(0x00a8, 0x00a8, 1, __NA_, 0, VF610_DSPI_SIN_PAD_CTRL), + VF610_PAD_PTB21__DSPI0_SOUT = IOMUX_PAD(0x00ac, 0x00ac, 1, __NA_, 0, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTB22__DSPI0_SCK = IOMUX_PAD(0x00b0, 0x00b0, 1, __NA_, 0, VF610_DSPI_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef..bd07758 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -124,6 +124,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) #define PAD_CTL_PKE (1 << 3) #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) +#define PAD_CTL_OBE (1 << 1) +#define PAD_CTL_IBE (1 << 0)
#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)