Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support

Dear Bo Shen,

On 02.07.12 05:35, Bo Shen wrote:

Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up

This patch is based on git://git.denx.de/u-boot-atmel.git

Please place this in comment section (after '---').

Signed-off-by: Bo Shen voice.shen@atmel.com

Changed since v1 Modify the code according to Andreas's suggestion

---

MAINTAINERS | 3 + arch/arm/cpu/arm926ejs/at91/Makefile | 1 + arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 237 +++++++++++++++ arch/arm/cpu/arm926ejs/at91/clock.c | 7 +- arch/arm/include/asm/arch-at91/at91sam9_matrix.h | 2 + arch/arm/include/asm/arch-at91/at91sam9x5.h | 172 +++++++++++ arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | 91 ++++++ arch/arm/include/asm/arch-at91/hardware.h | 2 + board/atmel/at91sam9x5ek/Makefile | 48 +++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 306 ++++++++++++++++++++ board/atmel/at91sam9x5ek/config.mk | 1 + boards.cfg | 1 + drivers/net/macb.c | 4 +- drivers/serial/atmel_usart.h | 7 +- include/configs/at91sam9x5ek.h | 201 +++++++++++++ 15 files changed, 1077 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5.h create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h create mode 100644 board/atmel/at91sam9x5ek/Makefile create mode 100644 board/atmel/at91sam9x5ek/at91sam9x5ek.c create mode 100644 board/atmel/at91sam9x5ek/config.mk create mode 100644 include/configs/at91sam9x5ek.h

diff --git a/MAINTAINERS b/MAINTAINERS index 6438e1c..a2fccbf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -660,6 +660,9 @@ Sedji Gaouaousedji.gaouaou@atmel.com at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC)

+Bo Shen voice.shen@atmel.com

• at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)

Simon Guinot simon.guinot@sequanux.org

inetspace_v2 ARM926EJS (Kirkwood SoC) diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index f333753..346e58f 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o COBJS-$(CONFIG_AT91_EFLASH) += eflash.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c new file mode 100644 index 0000000..2c99a4e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -0,0 +1,237 @@ +/*

• • Copyright (C) 2012 Atmel Corporation
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <../drivers/serial/atmel_usart.h>

+unsigned int get_chip_id(void) +{

• atmel_usart3_t *dbgu = (atmel_usart3_t *)ATMEL_BASE_DBGU;
• /* cidr is the same location with fidi */
• return readl(&dbgu->fidi) & ~AT91_CIDR_VERSION;

+}

+unsigned int get_extension_chip_id(void) +{

• atmel_usart3_t *dbgu = (struct atmel_usart3_t *)ATMEL_BASE_DBGU;

please use always the struct or leave it always, but not mixing the styles.

• /* ner is the same location with fidi */
• return readl(&dbgu->ner);

+}

NAK, I count this worse than before. a) including relative path b) cidr == fidi && ner == fidi ??; how about exid? c) struct atmel_usart3_t has same footprint in view of USART, but using that struct in this use case is wrong. If you fear to add some specific struct atmel_dbgu to arch specific includes please revert to first version with comment about the magic numbers.

+unsigned int has_emac1() +{

• return cpu_is_at91sam9x25();

+}

+unsigned int has_emac0() +{

• return !(cpu_is_at91sam9g15());

+}

+unsigned int has_lcdc() +{

• return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()

• || cpu_is_at91sam9x35();
  

+}

+char *get_cpu_name() +{

• unsigned int extension_id = get_extension_chip_id();
• if (cpu_is_at91sam9x5()) {

• switch (extension_id) {
  

• case ARCH_EXID_AT91SAM9G15:
  

• 	return CONFIG_SYS_AT91_G15_CPU_NAME;
  

• case ARCH_EXID_AT91SAM9G25:
  

• 	return CONFIG_SYS_AT91_G25_CPU_NAME;
  

• case ARCH_EXID_AT91SAM9G35:
  

• 	return CONFIG_SYS_AT91_G35_CPU_NAME;
  

• case ARCH_EXID_AT91SAM9X25:
  

• 	return CONFIG_SYS_AT91_X25_CPU_NAME;
  

• case ARCH_EXID_AT91SAM9X35:
  

• 	return CONFIG_SYS_AT91_X35_CPU_NAME;
  

• default:
  

• 	return CONFIG_SYS_AT91_UNKNOWN_CPU;
  

• }
  

• } else {

• return CONFIG_SYS_AT91_UNKNOWN_CPU;
  

• }

+}

+void at91_seriald_hw_init(void) +{

• at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
• at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
• at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
• writel(1 << ATMEL_ID_SYS, &pmc->pcer);

+}

+void at91_serial0_hw_init(void) +{

• at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
• at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
• at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
• writel(1 << ATMEL_ID_USART0, &pmc->pcer);

+}

+void at91_serial1_hw_init(void) +{

• at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
• at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
• at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
• writel(1 << ATMEL_ID_USART1, &pmc->pcer);

+}

+void at91_serial2_hw_init(void) +{

• at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
• at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
• at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
• writel(1 << ATMEL_ID_USART2, &pmc->pcer);

+}

+#ifdef CONFIG_ATMEL_SPI +void at91_spi0_hw_init(unsigned long cs_mask) +{

• at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE;
• at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
• at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
• at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
• /* Enable clock */
• writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
• if (cs_mask & (1 << 0))

• at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
  

• if (cs_mask & (1 << 1))

• at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
  

• if (cs_mask & (1 << 2))

• at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
  

• if (cs_mask & (1 << 3))

• at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
  

• if (cs_mask & (1 << 4))

• at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
  

• if (cs_mask & (1 << 5))

• at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
  

• if (cs_mask & (1 << 6))

• at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
  

• if (cs_mask & (1 << 7))

• at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
  

+}

+void at91_spi1_hw_init(unsigned long cs_mask) +{

• at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE;
• at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
• at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
• at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
• /* Enable clock */
• writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
• if (cs_mask & (1 << 0))

• at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
  

• if (cs_mask & (1 << 1))

• at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
  

• if (cs_mask & (1 << 2))

• at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
  

• if (cs_mask & (1 << 3))

• at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
  

• if (cs_mask & (1 << 4))

• at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
  

• if (cs_mask & (1 << 5))

• at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
  

• if (cs_mask & (1 << 6))

• at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
  

• if (cs_mask & (1 << 7))

• at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
  

+} +#endif

+#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{

• struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
• if (has_emac0()) {

• /* Enable EMAC0 clock */
  

• writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  

• /* EMAC0 pins setup */
  

• at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* ETXCK */
  

• at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* ERXDV */
  

• at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ERX0 */
  

• at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* ERX1 */
  

• at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ERXER */
  

• at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ETXEN */
  

• at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ETX0 */
  

• at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* ETX1 */
  

• at91_set_a_periph(AT91_PIO_PORTB, 5, 0);	/* EMDIO */
  

• at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* EMDC */
  

• }
• if (has_emac1()) {

• /* Enable EMAC1 clock */
  

• writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
  

• /* EMAC1 pins setup */
  

• at91_set_b_periph(AT91_PIO_PORTC, 29, 0);	/* ETXCK */
  

• at91_set_b_periph(AT91_PIO_PORTC, 28, 0);	/* ECRSDV */
  

• at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ERXO */
  

• at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ERX1 */
  

• at91_set_b_periph(AT91_PIO_PORTC, 16, 0);	/* ERXER */
  

• at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ETXEN */
  

• at91_set_b_periph(AT91_PIO_PORTC, 18, 0);	/* ETX0 */
  

• at91_set_b_periph(AT91_PIO_PORTC, 19, 0);	/* ETX1 */
  

• at91_set_b_periph(AT91_PIO_PORTC, 31, 0);	/* EMDIO */
  

• at91_set_b_periph(AT91_PIO_PORTC, 30, 0);	/* EMDC */
  

• }

+#ifndef CONFIG_RMII

• /* Only emac0 support MII */
• if (has_emac0()) {

• at91_set_b_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
  

• at91_set_b_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
  

• at91_set_b_periph(AT91_PIO_PORTB, 13,  0);	/* ERX2 */
  

• at91_set_b_periph(AT91_PIO_PORTB, 14,  0);	/* ERX3 */
  

• at91_set_b_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
  

• at91_set_b_periph(AT91_PIO_PORTB, 11,  0);	/* ETX2 */
  

• at91_set_b_periph(AT91_PIO_PORTB, 12,  0);	/* ETX3 */
  

• at91_set_b_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
  

• }

+#endif +} +#endif diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index a7085de..4d09542 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -154,7 +154,8 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = readl(&pmc->mckr); -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \

• || defined(CONFIG_AT91SAM9X5)
  

  /* plla divisor by 2 */ gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));

#endif @@ -168,7 +169,9 @@ int at91_clock_init(unsigned long main_clock) freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; if (mckr & AT91_PMC_MCKR_MDIV_MASK) freq /= 2; /* processor clock division */ -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)

• /* mck divisor by 2 */

I think this is also wrong here, it may be mck/2 or mck/4 or am I wrong?

+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \

• || defined(CONFIG_AT91SAM9X5)
  

  gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) ? freq / 3

diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h index 6d97189..b9a93b0 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h @@ -23,6 +23,8 @@ #include <asm/arch/at91cap9_matrix.h> #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #include <asm/arch/at91sam9g45_matrix.h> +#elif defined(CONFIG_AT91SAM9X5) +#include <asm/arch/at91sam9x5_matrix.h> #else #error "Unsupported AT91SAM9/CAP9 processor" #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h new file mode 100644 index 0000000..30bad24 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -0,0 +1,172 @@ +/*

• • Chip-specific header file for the AT91SAM9x5 family
• • Copyright (C) 2012 Atmel Corporation.
• • Definitions for the SoC:
• • AT91SAM9x5
• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License as published by
• • the Free Software Foundation; either version 2 of the License, or
• • (at your option) any later version.
• */

+#ifndef AT91SAM9X5_H +#define AT91SAM9X5_H

+/*

• • Peripheral identifiers/interrupts.
• */

+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */

+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */ +#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */ +#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD) */ +#define ATMEL_ID_USART0 5 /* USART 0 */ +#define ATMEL_ID_USART1 6 /* USART 1 */ +#define ATMEL_ID_USART2 7 /* USART 2 */ +#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */ +#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */ +#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */ +#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */ +#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_UART0 15 /* UART 0 */ +#define ATMEL_ID_UART1 16 /* UART 1 */ +#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_ADC 19 /* ADC Controller */ +#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */ +#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ +#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */ +#define ATMEL_ID_LCDC 25 /* LCD Controller */ +#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */ +#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */ +#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ +#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */

+/*

• • User Peripheral physical base addresses.
• */

+#define ATMEL_BASE_SPI0 0xf0000000 +#define ATMEL_BASE_SPI1 0xf0004000 +#define ATMEL_BASE_HSMCI0 0xf0008000 +#define ATMEL_BASE_HSMCI1 0xf000c000 +#define ATMEL_BASE_SSC 0xf0010000 +#define ATMEL_BASE_CAN0 0xf8000000 +#define ATMEL_BASE_CAN1 0xf8004000 +#define ATMEL_BASE_TC0 0xf8008000 +#define ATMEL_BASE_TC1 0xf8008040 +#define ATMEL_BASE_TC2 0xf8008080 +#define ATMEL_BASE_TC3 0xf800c000 +#define ATMEL_BASE_TC4 0xf800c040 +#define ATMEL_BASE_TC5 0xf800c080 +#define ATMEL_BASE_TWI0 0xf8010000 +#define ATMEL_BASE_TWI1 0xf8014000 +#define ATMEL_BASE_TWI2 0xf8018000 +#define ATMEL_BASE_USART0 0xf801c000 +#define ATMEL_BASE_USART1 0xf8020000 +#define ATMEL_BASE_USART2 0xf8024000 +#define ATMEL_BASE_USART3 0xf8028000 +#define ATMEL_BASE_EMAC0 0xf802c000 +#define ATMEL_BASE_EMAC1 0xf8030000 +#define ATMEL_BASE_PWM 0xf8034000 +#define ATMEL_BASE_LCDC 0xf8038000 +#define ATMEL_BASE_UDPHS 0xf803c000 +#define ATMEL_BASE_UART0 0xf8040000 +#define ATMEL_BASE_UART1 0xf8044000 +#define ATMEL_BASE_ISI 0xf8048000 +#define ATMEL_BASE_ADC 0xf804c000 +#define ATMEL_BASE_SYS 0xffffc000

+/*

• • System Peripherals (offset from ATMEL_BASE_SYS)
• */

+#define ATMEL_BASE_MATRIX 0xffffde00 +#define ATMEL_BASE_PMECC 0xffffe000 +#define ATMEL_BASE_PMERRLOC 0xffffe600 +#define ATMEL_BASE_DDRSDRC 0xffffe800 +#define ATMEL_BASE_SMC 0xffffea00 +#define ATMEL_BASE_DMAC0 0xffffec00 +#define ATMEL_BASE_DMAC1 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PIOD 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffe00 +#define ATMEL_BASE_SHDWC 0xfffffe10 +#define ATMEL_BASE_PIT 0xfffffe30 +#define ATMEL_BASE_WDT 0xfffffe40 +#define ATMEL_BASE_GPBR 0xfffffe60 +#define ATMEL_BASE_RTC 0xfffffeb0

+/*

• • Internal Memory.
• */

+#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */ +#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */

+/* 9x5 series chip id definitions */ +#define ARCH_ID_AT91SAM9X5 0x819a05a0 +#define ARCH_EXID_AT91SAM9G15 0x00000000 +#define ARCH_EXID_AT91SAM9G35 0x00000001 +#define ARCH_EXID_AT91SAM9X35 0x00000002 +#define ARCH_EXID_AT91SAM9G25 0x00000003 +#define ARCH_EXID_AT91SAM9X25 0x00000004

+#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5) +#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \

• 	(get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
  

+#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \

• 	(get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
  

+#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \

• 	(get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
  

+#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \

• 	(get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
  

+#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \

• 	(get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
  

+/*

• • Cpu Name
• */

+#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15" +#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25" +#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35" +#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25" +#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35" +#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type" +#define ATMEL_CPU_NAME get_cpu_name()

+/*

• • Other misc defines
• */

+#define ATMEL_PIO_PORTS 5 +#define CPU_HAS_PIO3 +#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */

+/*

• • at91sam9x5 specific prototypes
• */

+#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_emac1(void); +unsigned int has_emac0(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif

+#endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h new file mode 100644 index 0000000..cbc350c --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h @@ -0,0 +1,91 @@ +/*

• • Matrix-centric header file for the AT91SAM9M1x family
• • Copyright (C) 2008 Atmel Corporation.

I guess you should adopt the copyright

• • Memory Controllers (MATRIX, EBI) - System peripherals registers.
• • Based on AT91SAM9G45 preliminary datasheet.

Ouch, that slipped through in last review. This is copied from at91sam9g45_matrix.h.

If at91sam9x5 matches at91sam9g45 why another include? If not please change the source of information (and include guards some lines down).

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License as published by
• • the Free Software Foundation; either version 2 of the License, or
• • (at your option) any later version.
• */

+#ifndef AT91SAM9G45_MATRIX_H +#define AT91SAM9G45_MATRIX_H

+#ifndef __ASSEMBLY__

+struct at91_matrix {

• u32 mcfg[16];
• u32 scfg[16];
• u32 pras[16][2];
• u32 mrcr; /* 0x100 Master Remap Control */
• u32 filler[7];
• u32 ebicsa;
• u32 filler4[47];
• u32 wpmr;
• u32 wpsr;

+};

+#endif /* __ASSEMBLY__ */

+#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) +#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) +#define AT91_MATRIX_ULBT_128 (7 << 0)

+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18

+#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 +#define AT91_MATRIX_M6PR_SHIFT 24 +#define AT91_MATRIX_M7PR_SHIFT 28

+#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ +#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ +#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ +#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */

+#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_RCB9 (1 << 9) +#define AT91_MATRIX_RCB10 (1 << 10)

+#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_DBPD_ON (0 << 9) +#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9) +#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_NFD0_ON_D0 (0 << 24) +#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) +#define AT91_MATRIX_MP_OFF (0 << 25) +#define AT91_MATRIX_MP_ON (1 << 25)

+#endif diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 85c2889..4c4ee70 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -37,6 +37,8 @@ # include <asm/arch/at91sam9rl.h> #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) # include <asm/arch/at91sam9g45.h> +#elif defined(CONFIG_AT91SAM9X5) +# include <asm/arch/at91sam9x5.h> #elif defined(CONFIG_AT91CAP9) # include <asm/arch/at91cap9.h> #elif defined(CONFIG_AT91X40) diff --git a/board/atmel/at91sam9x5ek/Makefile b/board/atmel/at91sam9x5ek/Makefile new file mode 100644 index 0000000..1c9a4b6 --- /dev/null +++ b/board/atmel/at91sam9x5ek/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop stelian@popies.net +# Lead Tech Design <www.leadtechdesign.com>

You should add your copyright here too.

+# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(BOARD).o

+COBJS-y += at91sam9x5ek.o

+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS))

+$(LIB): $(obj).depend $(OBJS) $(SOBJS)

• $(call cmd_link_o_target, $(OBJS) $(SOBJS))

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+######################################################################### diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c new file mode 100644 index 0000000..ff8c518 --- /dev/null +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -0,0 +1,306 @@ +/*

• • Copyright (C) 2012 Atmel Corporation
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <atmel_hlcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> +#endif +#ifdef CONFIG_ATMEL_SPI +#include <spi.h> +#endif

+DECLARE_GLOBAL_DATA_PTR;

+/* ------------------------------------------------------------------------- */ +/*

• • Miscelaneous platform dependent initialisations
• */

+#ifdef CONFIG_CMD_NAND +static void at91sam9x5ek_nand_hw_init(void) +{

• struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
• struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
• struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
• unsigned long csa;
• /* Enable CS3 */
• csa = readl(&matrix->ebicsa);
• csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
• writel(csa, &matrix->ebicsa);
• /* Configure SMC CS3 for NAND/SmartMedia */
• writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |

• AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  

• &smc->cs[3].setup);
  

• writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |

• AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  

• &smc->cs[3].pulse);
  

• writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),

• &smc->cs[3].cycle);
  

• writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |

• AT91_SMC_MODE_EXNW_DISABLE |
  

+#ifdef CONFIG_SYS_NAND_DBW_16

• AT91_SMC_MODE_DBW_16 |
  

+#else /* CONFIG_SYS_NAND_DBW_8 */

• AT91_SMC_MODE_DBW_8 |
  

+#endif

• AT91_SMC_MODE_TDF_CYCLE(3),
  

• &smc->cs[3].mode);
  

• writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
• /* Configure RDY/BSY */
• at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
• /* Enable NandFlash */
• at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
• at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
• at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
• at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
• at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 13, 1);

+} +#endif

+#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif

Since this is empty now I ask myself if we could remove CONFIG_RESET_PHY_R from board include and remove this function here?

+int board_eth_init(bd_t *bis) +{

• int rc = 0;

+#ifdef CONFIG_MACB

• if (has_emac0())

• rc = macb_eth_initialize(0,
  

• 	(void *)ATMEL_BASE_EMAC0, 0x00);
  

• if (has_emac1())

• rc = macb_eth_initialize(1,
  

• 	(void *)ATMEL_BASE_EMAC1, 0x00);
  

+#endif

• return rc;

+}

+#ifdef CONFIG_MACB +static void at91sam9x5ek_macb_hw_init(void) +{

• at91_macb_hw_init();

+} +#endif

This one could also be removed.

+#ifdef CONFIG_LCD +vidinfo_t panel_info = {

• .vl_col = 800,
• .vl_row = 480,
• .vl_clk = 24000000,
• .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
• .vl_bpix = LCD_BPP,
• .vl_tft = 1,
• .vl_clk_pol = 1,
• .vl_hsync_len = 128,
• .vl_left_margin = 64,
• .vl_right_margin = 64,
• .vl_vsync_len = 2,
• .vl_upper_margin = 22,
• .vl_lower_margin = 21,
• .mmio = ATMEL_BASE_LCDC,

+};

+void lcd_enable(void) +{

• if (has_lcdc())

• at91_set_a_periph(AT91_PIO_PORTC, 29, 1);	/* power up */
  

+}

+void lcd_disable(void) +{

• if (has_lcdc())

• at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* power down */
  

+}

+static void at91sam9x5ek_lcd_hw_init(void) +{

• struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
• if (has_lcdc()) {

• at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
  

• at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
  

• at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDHSYNC */
  

• at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDISP */
  

• at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
  

• at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDPCK */
  

• at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
  

• at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
  

• writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  

• }

+}

+#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{

• ulong dram_size, nand_size;
• int i;
• char temp[32];
• if (has_lcdc()) {

• lcd_printf("%s\n", U_BOOT_VERSION);
  

• lcd_printf("(C) 2012 ATMEL Corp\n");
  

• lcd_printf("at91support@atmel.com\n");
  

• lcd_printf("%s CPU at %s MHz\n",
  

• 	get_cpu_name(),
  

• 	strmhz(temp, get_cpu_clk_rate()));
  

• dram_size = 0;
  

• for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  

• 	dram_size += gd->bd->bi_dram[i].size;
  

• nand_size = 0;
  

• for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  

• 	nand_size += nand_info[i].size;
  

• lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
  

• 	dram_size >> 20,
  

• 	nand_size >> 20);
  

• }

+} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */

+/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{

• return bus == 0 && cs < 2;

+}

+void spi_cs_activate(struct spi_slave *slave) +{

• switch (slave->cs) {
• case 1:

• at91_set_gpio_output(AT91_PIN_PA7, 0);
  

• break;
  

• case 0:
• default:

• at91_set_gpio_output(AT91_PIN_PA14, 0);
  

• break;
  

• }

+}

+void spi_cs_deactivate(struct spi_slave *slave) +{

• switch (slave->cs) {
• case 1:

• at91_set_gpio_output(AT91_PIN_PA7, 1);
  

• break;
  

• case 0:
• default:

• at91_set_gpio_output(AT91_PIN_PA14, 1);
  

• break;
  

• }

+} +#endif /* CONFIG_ATMEL_SPI */

+int board_early_init_f(void) +{

• at91_seriald_hw_init();
• return 0;

+}

+int board_init(void) +{

• /* arch number of ATMELEK-Board */
• gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
• /* adress of boot parameters */
• gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

+#ifdef CONFIG_CMD_NAND

• at91sam9x5ek_nand_hw_init();

+#endif

+#ifdef CONFIG_ATMEL_SPI

• at91_spi0_hw_init(1 << 0);
• at91_spi0_hw_init(1 << 4);

+#endif

+#ifdef CONFIG_MACB

• at91sam9x5ek_macb_hw_init();

can't we just use 'at91_macb_hw_init()' here?

+#endif

+#ifdef CONFIG_LCD

• at91sam9x5ek_lcd_hw_init();

+#endif

• return 0;

+}

+int dram_init(void) +{

• gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,

• 			CONFIG_SYS_SDRAM_SIZE);
  

• return 0;

+} diff --git a/board/atmel/at91sam9x5ek/config.mk b/board/atmel/at91sam9x5ek/config.mk new file mode 100644 index 0000000..6589a12 --- /dev/null +++ b/board/atmel/at91sam9x5ek/config.mk @@ -0,0 +1 @@ +CONFIG_SYS_TEXT_BASE = 0x26f00000 diff --git a/boards.cfg b/boards.cfg index 9205070..c9bd1b3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -89,6 +89,7 @@ at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH +at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 4578467..8f55cdc 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -471,7 +471,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \

• defined(CONFIG_AT91SAM9XE)

• defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5) macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));

#else macb_writel(macb, USRIO, 0); @@ -480,7 +480,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \

• defined(CONFIG_AT91SAM9XE)

• defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5) macb_writel(macb, USRIO, MACB_BIT(CLKEN));

#else macb_writel(macb, USRIO, MACB_BIT(MII)); diff --git a/drivers/serial/atmel_usart.h b/drivers/serial/atmel_usart.h index 7e4b2c9..ad1d9f0 100644 --- a/drivers/serial/atmel_usart.h +++ b/drivers/serial/atmel_usart.h @@ -37,8 +37,8 @@ typedef struct atmel_usart3 { u32 rtor; u32 ttgr; u32 reserved0[5];

• u32 fidi;
• u32 ner;

• u32 fidi; /* cidr for dbgu */
• u32 ner; /* exid for dbgu */

NAK

u32 reserved1; u32 ifr; u32 man; @@ -289,6 +289,9 @@ typedef struct atmel_usart3 { /* Constants for FI_DI_RATIO */ #define USART3_FI_DI_RATIO_DISABLE 0

+/* chip revision mask */ +#define AT91_CIDR_VERSION 0x1f

NAK, this belongs to DBGU and not to USART. I think one of the specific hardware.h would be a good place for that.

/* Bit manipulation macros */ #define USART3_BIT(name) \ (1 << USART3_##name##_OFFSET) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h new file mode 100644 index 0000000..9aba52c --- /dev/null +++ b/include/configs/at91sam9x5ek.h @@ -0,0 +1,201 @@ +/*

• • Copyright (C) 2012 Atmel Corporation
• • Configuation settings for the AT91SAM9X5EK board.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __CONFIG_H__ +#define __CONFIG_H__

+#include <asm/hardware.h>

+/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000

+#define CONFIG_AT91SAM9X5EK +#define CONFIG_AT91FAMILY

+#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

Hmm ... who defined it before?

+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO

+/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO

+/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS

+/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV

+#define CONFIG_BOOTDELAY 3

+/*

• • BOOTP options
• */

+#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME

+/*

• • Command line configuration.
• */

+#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI

I cound BDI a really useful command, please let this one in. Undefining the rest is ok with me. But keep in mind that you remove commands other u-boot have, this may confuse users.

+#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_AUTOSCRIPT

CONFIG_CMD_AUTOSCRIPT is unknown, please remove

+#undef CONFIG_CMD_LOADS

+#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND

+/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */

+#define CONFIG_SYS_INIT_SP_ADDR \

• (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)

+/* DataFlash */ +#ifdef CONFIG_ATMEL_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SYS_MAX_DATAFLASH_BANKS +#endif

+/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH

+/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5

+#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif

+/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI

CONFIG_NET_MULTI was removed in 31a4f1e5b6ee9b6335f0313dce7637cef887f84f

+#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R

I think this one could be removed.

+#define CONFIG_MACB_SEARCH_PHY

+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */

+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x26e00000

+#ifdef CONFIG_SYS_USE_DATAFLASH

dataflash is not implemented currently, is it?

+/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_MONITOR_BASE (0x10000000 + 0x8400) +#define CONFIG_ENV_OFFSET 0x5000 +#define CONFIG_ENV_ADDR (0x10000000 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x3000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \

• 		"sf read 0x22000000 0x42000 0x300000; " \
  

• 		"bootm 0x22000000"
  

+#else /* CONFIG_SYS_USE_NANDFLASH */

+/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read.jffs2 " \

• 		"0x22000000 0x200000 0x300000; " \
  

• 		"bootm 0x22000000"
  

Well, you read from jffs but work with ubifs later on? Is that ok? BTW: I do not know 'nand read.jffs2', does this subcommand exist really?

+#endif

+#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \

• 		"mtdparts=atmel_nand:" \
  

• 		"8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
  

• 		"root=/dev/mtdblock1 rw " \
  

• 		"rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"
  

+#define CONFIG_BAUDRATE 115200

+#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \

• 			+ 16)
  

+#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER

+/*

• • Size of malloc() pool
• */

+#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)

+#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif

+#endif

I think a v3 should make it into the tree. Please send next days cause I plan to send the pull request end of this week at the latest.

Best regards

Andreas Bießmann