On later Allwinner SoCs, the watchdog hardware is by all means a separate hardware block, with its own address range and interrupt line.
Move the register definitions to a separate file to facilitate supporting newer SoCs.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/include/asm/arch-sunxi/timer.h | 17 +++-------------- arch/arm/include/asm/arch-sunxi/watchdog.h | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 14 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/watchdog.h
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index 58e14fd..8ed383e 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -11,14 +11,10 @@ #ifndef _SUNXI_TIMER_H_ #define _SUNXI_TIMER_H_
-#define WDT_CTRL_RESTART (0x1 << 0) -#define WDT_CTRL_KEY (0x0a57 << 1) -#define WDT_MODE_EN (0x1 << 0) -#define WDT_MODE_RESET_EN (0x1 << 1) - #ifndef __ASSEMBLY__
#include <linux/types.h> +#include <asm/arch/watchdog.h>
/* General purpose timer */ struct sunxi_timer { @@ -43,12 +39,6 @@ struct sunxi_64cnt { u32 hi; /* 0xa8 */ };
-/* Watchdog */ -struct sunxi_wdog { - u32 ctl; /* 0x90 */ - u32 mode; /* 0x94 */ -}; - /* Rtc */ struct sunxi_rtc { u32 ctl; /* 0x100 */ @@ -77,9 +67,8 @@ struct sunxi_timer_reg { struct sunxi_timer timer[6]; /* We have 6 timers */ u8 res2[16]; struct sunxi_avs avs; - struct sunxi_wdog wdog; - u8 res3[8]; - struct sunxi_64cnt cnt64; + struct sunxi_wdog wdog; /* 0x90 */ + struct sunxi_64cnt cnt64; /* 0xa0 */ u8 res4[0x58]; struct sunxi_rtc rtc; struct sunxi_alarm alarm; diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h new file mode 100644 index 0000000..5b755e3 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2014 + * Chen-Yu Tsai wens@csie.org + * + * Watchdog register definitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_WATCHDOG_H_ +#define _SUNXI_WATCHDOG_H_ + +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + +struct sunxi_wdog { + u32 ctl; /* 0x00 */ + u32 mode; /* 0x04 */ + u32 res[2]; +}; + +#endif /* _SUNXI_WATCHDOG_H_ */