This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/mach-omap2/omap3/Kconfig | 1 - board/isee/igep00x0/Kconfig | 12 -- board/isee/igep00x0/MAINTAINERS | 7 - board/isee/igep00x0/Makefile | 10 -- board/isee/igep00x0/common.c | 67 -------- board/isee/igep00x0/igep00x0.c | 258 ------------------------------ board/isee/igep00x0/igep00x0.h | 127 --------------- board/isee/igep00x0/spl.c | 63 -------- configs/igep0032_defconfig | 52 ------ configs/igep00x0_defconfig | 53 ------ include/configs/omap3_igep00x0.h | 135 ---------------- 11 files changed, 785 deletions(-) delete mode 100644 board/isee/igep00x0/Kconfig delete mode 100644 board/isee/igep00x0/MAINTAINERS delete mode 100644 board/isee/igep00x0/Makefile delete mode 100644 board/isee/igep00x0/common.c delete mode 100644 board/isee/igep00x0/igep00x0.c delete mode 100644 board/isee/igep00x0/igep00x0.h delete mode 100644 board/isee/igep00x0/spl.c delete mode 100644 configs/igep0032_defconfig delete mode 100644 configs/igep00x0_defconfig delete mode 100644 include/configs/omap3_igep00x0.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 04b6ffe574a..9bd07dd8c55 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -200,7 +200,6 @@ source "board/compulab/cm_t35/Kconfig" source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" -source "board/isee/igep00x0/Kconfig" source "board/overo/Kconfig" source "board/ti/am3517crane/Kconfig" source "board/pandora/Kconfig" diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig deleted file mode 100644 index aa46882b051..00000000000 --- a/board/isee/igep00x0/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP3_IGEP00X0 - -config SYS_BOARD - default "igep00x0" - -config SYS_VENDOR - default "isee" - -config SYS_CONFIG_NAME - default "omap3_igep00x0" - -endif diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS deleted file mode 100644 index d75d400eed0..00000000000 --- a/board/isee/igep00x0/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -IGEP00X0 BOARD -M: Enric Balletbo i Serra eballetbo@gmail.com -S: Maintained -F: board/isee/igep00x0/ -F: include/configs/omap3_igep00x0.h -F: configs/igep00x0_defconfig -F: configs/igep0032_defconfig diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile deleted file mode 100644 index e095bcada29..00000000000 --- a/board/isee/igep00x0/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifdef CONFIG_SPL_BUILD -obj-y := spl.o common.o -else -obj-y := igep00x0.o common.o -endif diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c deleted file mode 100644 index f5d62ffc2e5..00000000000 --- a/board/isee/igep00x0/common.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <common.h> -#include <twl4030.h> -#include <asm/io.h> -#include <asm/omap_mmc.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <jffs2/load_kernel.h> -#include <linux/mtd/rawnand.h> -#include "igep00x0.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - int loops = 100; - - /* find out flash memory type, assume NAND first */ - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - gpmc_init(); - - /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { - udelay(1); - if (--loops == 0) { - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - gpmc_init(); /* reinitialize for OneNAND */ - break; - } - } - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c deleted file mode 100644 index 367af82d4a1..00000000000 --- a/board/isee/igep00x0/igep00x0.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - */ -#include <common.h> -#include <status_led.h> -#include <dm.h> -#include <ns16550.h> -#include <twl4030.h> -#include <netdev.h> -#include <spl.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/onenand.h> -#include <jffs2/load_kernel.h> -#include <mtd_node.h> -#include <fdt_support.h> -#include "igep00x0.h" - -static const struct ns16550_platdata igep_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(igep_uart) = { - "ns16550_serial", - &igep_serial -}; - -/* - * Routine: get_board_revision - * Description: GPIO_28 and GPIO_129 are used to read board and revision from - * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from - * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because - * this functionality is shared by USB HOST. - * Once USB reset is applied, U-boot configures these pins as input pullup to - * detect board and revision: - * IGEP0020-RF = 0b00 - * IGEP0020-RC = 0b01 - * IGEP0030-RG = 0b10 - * IGEP0030-RE = 0b11 - */ -static int get_board_revision(void) -{ - int revision; - - gpio_request(IGEP0030_USB_TRANSCEIVER_RESET, - "igep0030_usb_transceiver_reset"); - gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0); - - gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection"); - gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION); - revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION); - gpio_free(GPIO_IGEP00X0_BOARD_DETECTION); - - gpio_request(GPIO_IGEP00X0_REVISION_DETECTION, - "igep00x0_revision_detection"); - gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION); - revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION); - gpio_free(GPIO_IGEP00X0_REVISION_DETECTION); - - gpio_free(IGEP0030_USB_TRANSCEIVER_RESET); - - return revision; -} - -int onenand_board_init(struct mtd_info *mtd) -{ - if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { - struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; - return 0; - } - return 1; -} - -#if defined(CONFIG_CMD_NET) -static void reset_net_chip(int gpio) -{ - if (!gpio_request(gpio, "eth nrst")) { - gpio_direction_output(gpio, 1); - udelay(1); - gpio_set_value(gpio, 0); - udelay(40); - gpio_set_value(gpio, 1); - mdelay(10); - } -} - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - }; - - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - reset_net_chip(64); -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#else -static inline void setup_net_chip(void) {} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -static int ft_enable_by_compatible(void *blob, char *compat, int enable) -{ - int off = fdt_node_offset_by_compatible(blob, -1, compat); - if (off < 0) - return off; - - if (enable) - fdt_status_okay(blob, off); - else - fdt_status_disabled(blob, off); - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - static const struct node_info nodes[] = { - { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, - { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, - }; - - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif - ft_enable_by_compatible(blob, "ti,omap2-nand", - gpmc_cs0_flash == MTD_DEV_TYPE_NAND); - ft_enable_by_compatible(blob, "ti,omap2-onenand", - gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND); - - return 0; -} -#endif - -void set_led(void) -{ - switch (get_board_revision()) { - case 0: - case 1: - gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led"); - gpio_direction_output(IGEP0020_GPIO_LED, 1); - break; - case 2: - case 3: - gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led"); - gpio_direction_output(IGEP0030_GPIO_LED, 0); - break; - default: - /* Should not happen... */ - break; - } -} - -void set_boardname(void) -{ - char rev[5] = { 'F','C','G','E', }; - int i = get_board_revision(); - - rev[i+1] = 0; - env_set("board_rev", rev + i); - env_set("board_name", i < 2 ? "igep0020" : "igep0030"); -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - t2_t *t2_base = (t2_t *)T2_BASE; - u32 pbias_lite; - - twl4030_power_init(); - - /* set VSIM to 1.8V */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, - TWL4030_PM_RECEIVER_VSIM_VSEL_18, - TWL4030_PM_RECEIVER_VSIM_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); - - /* set up dual-voltage GPIOs to 1.8V */ - pbias_lite = readl(&t2_base->pbias_lite); - pbias_lite &= ~PBIASLITEVMODE1; - pbias_lite |= PBIASLITEPWRDNZ1; - writel(pbias_lite, &t2_base->pbias_lite); - if (get_cpu_family() == CPU_OMAP36XX) - writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | - OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, - OMAP34XX_CTRL_WKUP_CTRL); - - setup_net_chip(); - - omap_die_id_display(); - - set_led(); - - set_boardname(); - - return 0; -} - -void board_mtdparts_default(const char **mtdids, const char **mtdparts) -{ - struct mtd_info *mtd = get_mtd_device(NULL, 0); - if (mtd) { - static char ids[24]; - static char parts[48]; - const char *linux_name = "omap2-nand"; - if (strncmp(mtd->name, "onenand0", 8) == 0) - linux_name = "omap2-onenand"; - snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); - snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", - linux_name, 4 * mtd->erasesize >> 10); - *mtdids = ids; - *mtdparts = parts; - } -} diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h deleted file mode 100644 index aa532acad95..00000000000 --- a/board/isee/igep00x0/igep00x0.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - */ -#ifndef _IGEP00X0_H_ -#define _IGEP00X0_H_ - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\ - MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ -#endif diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c deleted file mode 100644 index e092e1a418b..00000000000 --- a/board/isee/igep00x0/spl.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <jffs2/load_kernel.h> -#include <linux/mtd/rawnand.h> -#include "igep00x0.h" - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - int mfr, id, err = identify_nand_chip(&mfr, &id); - - timings->mr = MICRON_V_MR_165; - if (!err) { - switch (mfr) { - case NAND_MFR_HYNIX: - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - break; - case NAND_MFR_MICRON: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - break; - default: - /* Should not happen... */ - break; - } - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - } else { - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - } -} - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; - - return 0; -} -#endif diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig deleted file mode 100644 index 383648789c5..00000000000 --- a/configs/igep0032_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TARGET_OMAP3_IGEP00X0=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_SPL_EXT_SUPPORT is not set -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_ONENAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_UDC=y -CONFIG_USB_OMAP3=y -CONFIG_TWL4030_USB=y -CONFIG_FAT_WRITE=y -CONFIG_UBIFS_SILENCE_MSG=y -CONFIG_BCH=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig deleted file mode 100644 index f2989e34e12..00000000000 --- a/configs/igep00x0_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TARGET_OMAP3_IGEP00X0=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_SPL_EXT_SUPPORT is not set -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_ONENAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_UDC=y -CONFIG_USB_OMAP3=y -CONFIG_TWL4030_USB=y -CONFIG_FAT_WRITE=y -CONFIG_UBIFS_SILENCE_MSG=y -CONFIG_BCH=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h deleted file mode 100644 index b9d65697521..00000000000 --- a/include/configs/omap3_igep00x0.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common configuration settings for IGEP technology based boards - * - * (C) Copyright 2012 - * ISEE 2007 SL, <www.iseebcn.com> - */ - -#ifndef __IGEP00X0_H -#define __IGEP00X0_H - -#include <configs/ti_omap3_common.h> - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ -#undef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_TEXT_BASE 0x40200000 - -#define CONFIG_REVISION_TAG 1 - -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */ - -/* TPS65950 */ -#define PBIASLITEVMODE1 (1 << 8) - -/* LED */ -#define IGEP0020_GPIO_LED 27 -#define IGEP0030_GPIO_LED 16 - -/* Board and revision detection GPIOs */ -#define IGEP0030_USB_TRANSCEIVER_RESET 54 -#define GPIO_IGEP00X0_BOARD_DETECTION 28 -#define GPIO_IGEP00X0_REVISION_DETECTION 129 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "IGEP" - -#ifndef CONFIG_SPL_BUILD - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define MEM_LAYOUT_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "scriptaddr=0x87E00000\0" \ - "pxefile_addr_r=0x87F00000\0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include <config_distro_bootcmd.h> - -#define ENV_FINDFDT \ - "findfdt="\ - "if test ${board_name} = igep0020; then " \ - "if test ${board_rev} = F; then " \ - "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ - "else " \ - "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ - "if test ${board_name} = igep0030; then " \ - "if test ${board_rev} = G; then " \ - "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ - "else " \ - "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ - "if test ${fdtfile} = ''; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_FINDFDT \ - ENV_DEVICE_SETTINGS \ - MEM_LAYOUT_SETTINGS \ - BOOTENV - -#endif - -#define CONFIG_SYS_MTDPARTS_RUNTIME - -/* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) - -/* NAND config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW - -/* UBI configuration */ -#define CONFIG_SPL_UBI 1 -#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 -#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) -#define CONFIG_SPL_UBI_MAX_PEBS 4096 -#define CONFIG_SPL_UBI_VOL_IDS 8 -#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0 -#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3 -#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4 -#define CONFIG_SPL_UBI_PEB_OFFSET 4 -#define CONFIG_SPL_UBI_VID_OFFSET 512 -#define CONFIG_SPL_UBI_LEB_START 2048 -#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 - -/* environment organization */ -#define CONFIG_ENV_UBI_PART "UBI" -#define CONFIG_ENV_UBI_VOLUME "config" -#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" -#define CONFIG_ENV_SIZE (32*1024) - -#endif /* __IGEP00X0_H */