Mike Frysinger wrote:
On Tuesday 17 March 2009 14:18:13 Scott Wood wrote:
Mike Frysinger wrote:
[snip]
I don't know of any amount of "nop" instructions that would be architecturally guaranteed to avoid this -- they're no-ops, not syncs (despite how some other architectures use them). They can be discarded as fast as the chip can decode them.
right, it depends on the pipeline. some let the nops force the address decode stages to get filled so they dont get speculatively filled and then fetched. sounds like the ppc pipeline doesnt operate that way.
For the record, using NOPs to fill the pipeline is a poor solution because it is very implementation specific: you have to assume a certain implementation (how NOPs are processed and the depth of the pipeline) for this to work.
If you switched PowerPC processors (been known to happen) or, if Freescale ever made a Super Deluxe 100% Backward Compatible Version of your selected CPU with a deeper pipeline (never have that I know about, but we can dream...), the NOP method would mysteriously break again. Not only that, but it would mysteriously break 5 years or more from now when we've all forgotten what the fix was. The result would be that we would have to spend lots of energy resurrecting old boards, old compilers, and old code only to discover we were done in by assumptions.
As Scott so eloquently pointed out, /that's/ why there is a "guarded" bit. (OK ok, he actually pointed out "That's /why/ there is a guarded bit." ;-)
[snip]
thanks for the info -mike
Best regards, gvb