The IP supports two ports, A and B, each providing up to 32 gpios. The driver already creates a 2nd gpio bank by reading the 2nd node from DT, so this is quite a simple change to support the 2nd bank.
Signed-off-by: Phil Edworthy phil.edworthy@renesas.com --- drivers/gpio/dwapb_gpio.c | 40 +++++++++++++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 471e18a..dda0b42 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -21,6 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define GPIO_SWPORTA_DR 0x00 #define GPIO_SWPORTA_DDR 0x04 +#define GPIO_SWPORTB_DR 0x0C +#define GPIO_SWPORTB_DDR 0x10 #define GPIO_INTEN 0x30 #define GPIO_INTMASK 0x34 #define GPIO_INTTYPE_LEVEL 0x38 @@ -29,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_PORTA_DEBOUNCE 0x48 #define GPIO_PORTA_EOI 0x4c #define GPIO_EXT_PORTA 0x50 +#define GPIO_EXT_PORTB 0x54
struct gpio_dwapb_platdata { const char *name; @@ -41,7 +44,11 @@ static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin) { struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
- clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + if (plat->bank == 0) + clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTB_DDR, 1 << pin); + return 0; }
@@ -50,12 +57,21 @@ static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin, { struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
- setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + if (plat->bank == 0) + setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + else + setbits_le32(plat->base + GPIO_SWPORTB_DDR, 1 << pin);
if (val) - setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + if (plat->bank == 0) + setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + setbits_le32(plat->base + GPIO_SWPORTB_DR, 1 << pin); else - clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + if (plat->bank == 0) + clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTB_DR, 1 << pin);
return 0; } @@ -63,7 +79,11 @@ static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin, static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin) { struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); - return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin)); + + if (plat->bank == 0) + return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin)); + else + return !!(readl(plat->base + GPIO_EXT_PORTB) & (1 << pin)); }
@@ -72,9 +92,15 @@ static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val) struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
if (val) - setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + if (plat->bank == 0) + setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + setbits_le32(plat->base + GPIO_SWPORTB_DR, 1 << pin); else - clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + if (plat->bank == 0) + clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTB_DR, 1 << pin);
return 0; }