[U-Boot] [PATCH 17/23] x86: Define cache line size

This avoids a warning in the Realtek Ethernet driver. The value may not matter on x86.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h index 508b63f..fff1edd 100644 --- a/arch/x86/include/asm/cache.h +++ b/arch/x86/include/asm/cache.h @@ -7,6 +7,8 @@ #ifndef __X86_CACHE_H__ #define __X86_CACHE_H__

+#define CONFIG_SYS_CACHELINE_SIZE 16 + /* * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise * use 64-bytes, a safe default for x86.