In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table.
Reserve the space above the stack and use gd->irq_sp as storage for the exception base address.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com ---
arch/mips/lib/Makefile | 1 + arch/mips/lib/stack.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/mips/lib/stack.c
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index b7ce5df..02607f7 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -7,6 +7,7 @@
obj-y += cache.o obj-y += cache_init.o +obj-y += stack.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/mips/lib/stack.c b/arch/mips/lib/stack.c new file mode 100644 index 0000000..c80f5fe --- /dev/null +++ b/arch/mips/lib/stack.c @@ -0,0 +1,19 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_reserve_stacks(void) +{ + /* reserve space for exception vector table */ + gd->start_addr_sp -= 0x500; + gd->start_addr_sp &= ~0xFFF; + gd->irq_sp = gd->start_addr_sp; + debug("Reserving %d Bytes for exception vector at: %08lx\n", + 0x500, gd->start_addr_sp); + + return 0; +}