
6 Apr
2017
6 Apr
'17
5:25 p.m.
On 03/28/2017 01:51 PM, Ken Lin wrote:
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin yungching0725@gmail.com
Acked-by: Akshay Bhat akshay.bhat@timesys.com