Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU

Hi again Andre,

On 12/5/22 17:45, Andre Przywara wrote:

+static struct ccu_clk_gate d1_gates[] = {

• [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
• [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
• [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
• [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
• [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
• [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
• [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
• [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
• [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
• [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
• [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
• [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
• [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
• [CLK_SPI0] = GATE(0x940, BIT(31)),
• [CLK_SPI1] = GATE(0x944, BIT(31)),
• [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
• [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
• [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
• [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
• [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
• [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
• [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
• [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
• [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
• [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
• [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
• [CLK_RISCV] = GATE(0xd04, BIT(31)),

+};

Would it be reasonable to add (possibly one for APB1 also): [CLK_APB0] = GATE_DUMMY,

...in order to suppress this warning at init: sunxi_set_gate: (CLK#24) unhandled

As I understand it, CLK_APB0 is only for speed control and doesn't have a gate, but since the FDT references it, other drivers are asking the clock driver to ungate it, resulting in that (safe-to-ignore) warning.

Warm regards, Sam

PS: Do you have any plans for PSCI support, so we can get the second core up too? I'd like to patch that in and include it in your series once my available time permits. Just thought I'd check that you/someone wasn't working on it already. :)