From: Richard Zhu hongxing.zhu@nxp.com
Add the PCIe support on i.MX8MM platforms.
Signed-off-by: Richard Zhu hongxing.zhu@nxp.com Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com Reviewed-by: Tim Harvey tharvey@gateworks.com Tested-by: Tim Harvey tharvey@gateworks.com Signed-off-by: Shawn Guo shawnguo@kernel.org Signed-off-by: Marek Vasut marex@denx.de # Pick from Linux 854a4766ac12 ("arm64: dts: imx8mm: Add the pcie support") --- arch/arm/dts/imx8mm.dtsi | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 63cab127c4c..724f6ddbf39 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -510,7 +510,7 @@ };
gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };
@@ -1085,6 +1085,37 @@ status = "disabled"; };
+ pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie"; + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + linux,pci-domain = <0>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */