From: Nagabhushana Netagunte nagabhushana.netagunte@ti.com
add support for dm365 in speed.c file to use appropriate PLL clocks to calculate cpu frequency and print.
Signed-off-by: sugumar sugumar@ti.com Signed-off-by: Nagabhushana Netagunte nagabhushana.netagunte@ti.com --- arch/arm/cpu/arm926ejs/davinci/speed.c | 44 +++++++++++++++++++++++++++---- 1 files changed, 38 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c index ebcd212..8650061 100644 --- a/arch/arm/cpu/arm926ejs/davinci/speed.c +++ b/arch/arm/cpu/arm926ejs/davinci/speed.c @@ -50,6 +50,13 @@ #define DDR_PLLDIV PLLC_PLLDIV1 #endif
+#ifdef CONFIG_SOC_DM365 +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DDR_PLLDIV PLLC_PLLDIV7 +#define SYSTEM_MOD 0x01C40000 +#define PERL_CTRL 0x48 +#endif + #ifdef CONFIG_SOC_DM644X #define ARM_PLLDIV PLLC_PLLDIV2 #define DSP_PLLDIV PLLC_PLLDIV1 @@ -129,12 +136,14 @@ static unsigned pll_div(volatile void *pllbase, unsigned offset)
static inline unsigned pll_prediv(volatile void *pllbase) { -#ifdef CONFIG_SOC_DM355 +#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365) /* this register read seems to fail on pll0 */ if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) return 8; else return pll_div(pllbase, PLLC_PREDIV); +#elif defined(CONFIG_SOC_DM365) + return pll_div(pllbase, PLLC_PREDIV); #endif return 1; } @@ -162,7 +171,11 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) /* the PLL might be bypassed */ if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { base /= pll_prediv(pllbase); - base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); +#ifdef CONFIG_SOC_DM365 + base *= (2 * (REG(pllbase + PLLC_PLLM) & 0x3ff)); +#else + base *= (1 + (REG(pllbase + PLLC_PLLM) & 0x0ff)); +#endif base /= pll_postdiv(pllbase); } return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); @@ -181,18 +194,37 @@ int showclocks(cmd_tbl_t *cmdtp, /* REVISIT fetch and display CPU ID and revision information * too ... that will matter as more revisions appear. */ - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); + unsigned int pllbase; + unsigned int sysdiv; + + pllbase = DAVINCI_PLL_CNTRL0_BASE; + sysdiv = ARM_PLLDIV; +#ifdef CONFIG_SOC_DM365 + pllbase = (REG(SYSTEM_MOD + PERL_CTRL) & BIT(29)) ? + DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE; +#endif + + printf("Cores: ARM %d MHz", pll_sysclk_mhz(pllbase, sysdiv));
#ifdef DSP_PLLDIV printf(", DSP %d MHz", pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); #endif
+ pllbase = DAVINCI_PLL_CNTRL1_BASE; + sysdiv = DDR_PLLDIV; + +#ifdef CONFIG_SOC_DM365 + pllbase = (REG(SYSTEM_MOD + PERL_CTRL) & BIT(27)) ? + DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE; + + if (pllbase == DAVINCI_PLL_CNTRL1_BASE) + sysdiv = PLLC_PLLDIV3; +#endif + printf("\nDDR: %d MHz\n", /* DDR PHY uses an x2 input clock */ - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) - / 2); + pll_sysclk_mhz(pllbase, sysdiv)/2); return 0;
}