The sun50i platform (e.g. the A64/sun50iw1p1) integrates 2 USB PHYs which are connected as follows: PHY#0 is shared between the OTG controller (MUSB) [at 01C19000] and the USB-OTG-HCI [at 01C1A000] PHY#1 is dedicated to USB-HCI0 [at 01C1B000] and can be bypassed when connecting HCI0 to the HSIC interface
Note that all USB PHYs are controlled from within the OTG address space at 01C19000.
X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- drivers/usb/musb-new/musb_regs.h | 2 +- include/configs/sun50i.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 0f18dd7..da474f0 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -434,12 +434,12 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
static inline u8 musb_read_configdata(void __iomem *mbase) { -#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T +#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T || defined CONFIG_MACH_SUN50I /* <Sigh> allwinner saves a reg, and we need to hardcode this */ return 0xde; #else musb_writeb(mbase, MUSB_INDEX, 0); return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA); #endif }
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 3e5708b..02888d3 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -1,30 +1,30 @@ /* * Configuration settings for the Allwinner A64 (sun50i) CPU * * SPDX-License-Identifier: GPL-2.0+ */
#ifndef __CONFIG_H #define __CONFIG_H
/* * A64 specific configuration */
#ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif
-#define CONFIG_SUNXI_USB_PHYS 1 +#define CONFIG_SUNXI_USB_PHYS 2
#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
/* * Include common sunxi configuration where most the settings are */ #include <configs/sunxi-common.h>
#endif /* __CONFIG_H */