This is architecture-dependent early initialization hence should be put in the platform Kconfig.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Andy Shevchenko andy.shevchenko@gmail.com ---
Changes in v2: None
arch/x86/cpu/broadwell/Kconfig | 1 + arch/x86/cpu/broadwell/refcode.c | 17 ++++++++++++++++- arch/x86/cpu/qemu/Kconfig | 1 + arch/x86/cpu/quark/Kconfig | 1 + arch/x86/cpu/queensbay/Kconfig | 1 + arch/x86/include/asm/cpu.h | 12 ------------ .../advantech/som-db5800-som-6867/som-db5800-som-6867.c | 5 ----- .../conga-qeval20-qa3-e3845/conga-qeval20-qa3.c | 5 ----- board/coreboot/coreboot/Makefile | 2 +- board/coreboot/coreboot/coreboot.c | 14 -------------- board/efi/efi-x86/efi.c | 6 ------ board/google/chromebook_link/link.c | 11 ----------- board/google/chromebook_samus/samus.c | 6 ------ board/google/chromebox_panther/panther.c | 6 ------ board/intel/minnowmax/minnowmax.c | 5 ----- common/Kconfig | 1 - configs/bayleybay_defconfig | 1 - configs/cougarcanyon2_defconfig | 1 - configs/dfi-bt700-q7x-151_defconfig | 1 - configs/edison_defconfig | 1 - configs/efi-x86_defconfig | 1 - configs/theadorable-x86-dfi-bt700_defconfig | 1 - 22 files changed, 21 insertions(+), 79 deletions(-) delete mode 100644 board/coreboot/coreboot/coreboot.c
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig index 8501949..f3006c3 100644 --- a/arch/x86/cpu/broadwell/Kconfig +++ b/arch/x86/cpu/broadwell/Kconfig @@ -6,6 +6,7 @@ config INTEL_BROADWELL bool select CACHE_MRC_BIN + select ARCH_EARLY_INIT_R imply HAVE_INTEL_ME
if INTEL_BROADWELL diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 436c6c4..4fa4de3 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -56,7 +56,17 @@ struct rmodule_header { uint32_t padding[4]; } __packed;
-int cpu_run_reference_code(void) +/** + * cpu_run_reference_code() - Run the platform reference code + * + * Some platforms require a binary blob to be executed once SDRAM is + * available. This is used to set up various platform features, such as the + * platform controller hub (PCH). This function should be implemented by the + * CPU-specific code. + * + * @return 0 on success, -ve on failure + */ +static int cpu_run_reference_code(void) { struct pei_data _pei_data __aligned(8); struct pei_data *pei_data = &_pei_data; @@ -111,3 +121,8 @@ int cpu_run_reference_code(void)
return 0; } + +int arch_early_init_r(void) +{ + return cpu_run_reference_code(); +} diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index 6808c9a..6f61744 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -6,6 +6,7 @@
config QEMU bool + select ARCH_EARLY_INIT_R
if QEMU
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 641aa22..9e7d983 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -7,6 +7,7 @@ config INTEL_QUARK bool select HAVE_RMU + select ARCH_EARLY_INIT_R select ARCH_MISC_INIT
if INTEL_QUARK diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 6136d75..e2dfe19 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -8,6 +8,7 @@ config INTEL_QUEENSBAY bool select HAVE_FSP select HAVE_CMC + select ARCH_EARLY_INIT_R
if INTEL_QUEENSBAY
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index c00687a..bc2c4ff 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -288,16 +288,4 @@ u32 cpu_get_family_model(void); */ u32 cpu_get_stepping(void);
-/** - * cpu_run_reference_code() - Run the platform reference code - * - * Some platforms require a binary blob to be executed once SDRAM is - * available. This is used to set up various platform features, such as the - * platform controller hub (PCH). This function should be implemented by the - * CPU-specific code. - * - * @return 0 on success, -ve on failure - */ -int cpu_run_reference_code(void); - #endif diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 5bed2c1..6158795 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -17,8 +17,3 @@ int board_early_init_f(void)
return 0; } - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 7a5b765..1283eeb 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -28,11 +28,6 @@ int board_early_init_f(void) return 0; }
-int arch_early_init_r(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 27ebe78..4f2ac89 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y += coreboot_start.o coreboot.o +obj-y += coreboot_start.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c deleted file mode 100644 index bb7f778..0000000 --- a/board/coreboot/coreboot/coreboot.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <cros_ec.h> -#include <asm/gpio.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c index 1fbe36a..2adc202 100644 --- a/board/efi/efi-x86/efi.c +++ b/board/efi/efi-x86/efi.c @@ -5,9 +5,3 @@ */
#include <common.h> -#include <asm/gpio.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 64e7c1a..dc22592 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -5,14 +5,3 @@ */
#include <common.h> -#include <cros_ec.h> -#include <dm.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c index 356b92a..5b5eb19 100644 --- a/board/google/chromebook_samus/samus.c +++ b/board/google/chromebook_samus/samus.c @@ -5,9 +5,3 @@ */
#include <common.h> -#include <asm/cpu.h> - -int arch_early_init_r(void) -{ - return cpu_run_reference_code(); -} diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index ed60e44..2adc202 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -5,9 +5,3 @@ */
#include <common.h> -#include <asm/arch/pch.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 99aed53..5bdb2fd 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -12,11 +12,6 @@
#define GPIO_BANKE_NAME "gpioe"
-int arch_early_init_r(void) -{ - return 0; -} - int misc_init_r(void) { struct udevice *dev; diff --git a/common/Kconfig b/common/Kconfig index d005a3b..e1bbf44 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -858,7 +858,6 @@ menu "Start-up hooks"
config ARCH_EARLY_INIT_R bool "Call arch-specific init soon after relocation" - default y if X86 help With this option U-Boot will call arch_early_init_r() soon after relocation. Driver model is running by this point, and the cache diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 9436784..bf00390 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -15,7 +15,6 @@ CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 2e729fa..84856aa 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -5,7 +5,6 @@ CONFIG_TARGET_COUGARCANYON2=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index bed4f28..76cdf55 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -15,7 +15,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set diff --git a/configs/edison_defconfig b/configs/edison_defconfig index ba43b47..02c09aa 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -3,7 +3,6 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="edison" CONFIG_TARGET_EDISON=y CONFIG_SMP=y -# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index 20681b0..7495da4 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -7,7 +7,6 @@ CONFIG_FIT=y CONFIG_ENV_IS_NOWHERE=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 64af353..dee551b 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -15,7 +15,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set