Re: [U-Boot] [PATCH 23/30] riscv: do not blindly modify the mstatus CSR

On Sat, Oct 20, 2018 at 6:11 AM Lukas Auer lukas.auer@aisec.fraunhofer.de wrote:

The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for u-boot to run. Remove it.

nits: U-Boot

This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register.

Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de

arch/riscv/cpu/start.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)

Reviewed-by: Bin Meng bmeng.cn@gmail.com