Dear Stefan,
In message 200809231237.12323.yur@emcraft.com Yuri Tikhonov wrote:
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results.
Signed-off-by: Yuri Tikhonov yur@emcraft.com
cpu/ppc4xx/44x_spd_ddr2.c | 10 ++++++---- include/asm-ppc/ppc4xx-sdram.h | 5 +++++ 2 files changed, 11 insertions(+), 4 deletions(-)
I must admit that I lost track in the discussion following this posting what the real state of affairs is now. Do we need to change anything in U-Boot, or not, and why not?
Best regards,
Wolfgang Denk