Add ECSPI clock entries to iMX8MN clock driver. Only make those entries available in case SPI support in U-Boot is enabled at all to conserve space, esp. in SPL.
Signed-off-by: Marek Vasut marex@denx.de Cc: Peng Fan peng.fan@nxp.com Cc: Stefano Babic sbabic@denx.de --- drivers/clk/imx/clk-imx8mn.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index e29d902544c..e398d7de02a 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -105,6 +105,20 @@ static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+#if CONFIG_IS_ENABLED(DM_SPI) +static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; +#endif + static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
@@ -440,6 +454,21 @@ static int imx8mn_clk_probe(struct udevice *dev) base + 0x40a0, 0)); #endif
+#if CONFIG_IS_ENABLED(DM_SPI) + clk_dm(IMX8MN_CLK_ECSPI1, + imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280)); + clk_dm(IMX8MN_CLK_ECSPI2, + imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300)); + clk_dm(IMX8MN_CLK_ECSPI3, + imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180)); + clk_dm(IMX8MN_CLK_ECSPI1_ROOT, + imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + clk_dm(IMX8MN_CLK_ECSPI2_ROOT, + imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + clk_dm(IMX8MN_CLK_ECSPI3_ROOT, + imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); +#endif + return 0; }