[U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap()

The most significant bit in mcause register should be masked to form the exception code for _exit_trap().

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/riscv/lib/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index c568706..5e09196 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -73,7 +73,7 @@ ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) timer_interrupt(0); /* handle_m_timer_interrupt */ else - _exit_trap(mcause, epc, regs); + _exit_trap(mcause & MCAUSE_CAUSE, epc, regs);

return epc; }