Due to a hardware bug mentioned in latest AP7000 datasheet errata (revision M from 09.09) branch folding is unreliable. This patch disables CPUCR.FE bitfield as stated in datasheet.
Signed-off-by: Andreas Bießmann biessmann@corscience.de ---
Changes since v1: - fix comment
arch/avr32/cpu/start.S | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/avr32/cpu/start.S b/arch/avr32/cpu/start.S index d37a46e..99c9e06 100644 --- a/arch/avr32/cpu/start.S +++ b/arch/avr32/cpu/start.S @@ -27,9 +27,10 @@ #define SYSREG_MMUCR_S_OFFSET 4
#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0)) -#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \ - | SYSREG_BIT(FE) | SYSREG_BIT(RE) \ - | SYSREG_BIT(IBE) | SYSREG_BIT(IEE)) +/* due to errata (unreliable branch folding) clear FE bit explicitly */ +#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE) \ + | SYSREG_BIT(RE) | SYSREG_BIT(IBE) \ + | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
/* * To save some space, we use the same entry point for