Commit c09d29057a and df120142f36 break kernel loading on rock2 board.
console output: Starting kernel ...
### ERROR ### Please RESET the board ###
This reverts commit df120142f36b6ff8b12187b8860269763b2b3203.
Conflicts: arch/arm/cpu/armv7/cache_v7.c arch/arm/cpu/armv7/cache_v7_asm.S
Signed-off-by: Sandy Patterson apatterson@sightlogix.com ---
arch/arm/cpu/armv7/cache_v7.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 9fbabb4..e72bed5 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -10,8 +10,10 @@ #include <asm/armv7.h> #include <asm/utils.h>
-#define ARMV7_DCACHE_INVAL_RANGE 1 -#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2 +#define ARMV7_DCACHE_INVAL_ALL 1 +#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2 +#define ARMV7_DCACHE_INVAL_RANGE 3 +#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
#ifndef CONFIG_SYS_DCACHE_OFF
@@ -19,6 +21,18 @@ void v7_flush_dcache_all(void); void v7_invalidate_dcache_all(void);
+/* + * Write the level and type you want to Cache Size Selection Register(CSSELR) + * to get size details from Current Cache Size ID Register(CCSIDR) + */ +static void set_csselr(u32 level, u32 type) +{ + u32 csselr = level << 1 | type; + + /* Write to Cache Size Selection Register(CSSELR) */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); +} + static u32 get_ccsidr(void) { u32 ccsidr; @@ -207,7 +221,7 @@ static void v7_inval_tlb(void)
void invalidate_dcache_all(void) { - v7_invalidate_dcache_all(); + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
v7_outer_cache_inval_all(); }