On 20.08.24 11:37, Mayuresh Chitale wrote:
Define CBO inval and flush instructions and use those for the dcache inval and flush operations respectively.
Signed-off-by: Mayuresh Chitale mchitale@ventanamicro.com
arch/riscv/Kconfig | 4 ++ arch/riscv/include/asm/cache.h | 3 ++ arch/riscv/lib/cache.c | 90 ++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c52..0f89d07be7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -310,6 +310,10 @@ endmenu config RISCV_ISA_A def_bool y
+config RISCV_ISA_ZICBOM
- bool "Zicbom support"
- depends on !SYS_DISABLE_DCACHE_OPS
- config DMA_ADDR_T_64BIT bool default y if 64BIT
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 874963d731..42dbce5b4f 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -9,6 +9,9 @@
/* cache */ void cache_flush(void); +void riscv_zicbom_init(void); +void cbo_flush(unsigned long start, unsigned long end); +void cbo_inval(unsigned long start, unsigned long end);
/*
- The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index afad7e117f..456353d9c1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -5,6 +5,95 @@ */
#include <cpu_func.h> +#include <dm.h> +#include <asm/insn-def.h> +#include <linux/const.h>
+#define CBO_INVAL(base) \
- INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
RS1(base), SIMM12(0))+#define CBO_CLEAN(base) \
- INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
RS1(base), SIMM12(1))+#define CBO_FLUSH(base) \
- INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
RS1(base), SIMM12(2))+enum {
- CBO_CLEAN,
- CBO_FLUSH,
- CBO_INVAL
+} riscv_cbo_ops; +static int zicbom_block_size;
+static inline void do_cbo_clean(unsigned long base) +{
- asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) ::
"r"(base) : "memory");+}
+static inline void do_cbo_flush(unsigned long base) +{
- asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) ::
"r"(base) : "memory");+}
+static inline void do_cbo_inval(unsigned long base) +{
- asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) ::
"r"(base) : "memory");+}
+static void cbo_op(int op_type, unsigned long start,
unsigned long end)+{
- unsigned long op_size = end - start, size = 0;
- void (*fn)(unsigned long base);
- switch (op_type) {
- case CBO_CLEAN:
fn = do_cbo_clean;break;- case CBO_FLUSH:
fn = do_cbo_flush;break;- case CBO_INVAL:
fn = do_cbo_inval;break;- }
- start &= ~(UL(zicbom_block_size - 1));
- while (size < op_size) {
fn(start + size);size += zicbom_block_size;- }
+}
+void cbo_flush(unsigned long start, unsigned long end) +{
- if (zicbom_block_size)
cbo_op(CBO_FLUSH, start, end);+}
+void cbo_inval(unsigned long start, unsigned long end) +{
- if (zicbom_block_size)
cbo_op(CBO_INVAL, start, end);+}
+void riscv_zicbom_init(void) +{
- struct udevice *dev;
- if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM))
return;- uclass_first_device(UCLASS_CPU, &dev);
- if (!dev) {
log_err("Failed to get cpu device!\n");return;
Please, return an error code.
- }
- (void)dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size);
Please, do not ignore errors.
Best regards
Heinrich
+}
void invalidate_icache_all(void) { @@ -72,4 +161,5 @@ __weak int dcache_status(void)
__weak void enable_caches(void) {
- puts("WARNING: Caches not enabled\n"); }