The SPL for socfpga gen5 currently takes all peripherals out of reset unconditionally. To implement proper reset handling for peripherals, the reset node has to be provided with the SPL dts.
In preparation to move the DDR driver to DM, the sdr node is required in SPL, too.
This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon files so that the reset manager and SDR driver correctly probe in SPL. It centralizes these settings into a common file since in contrast to boot-type specific nodes, "soc", "rst" and "sdr" are always needed.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v3: - centralize u-boot,dem-pre-reloc for soc, rst and sdr into one common file
Changes in v2: None
arch/arm/dts/socfpga-common-u-boot.dtsi | 19 +++++++++++++++++++ arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 6 ++---- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +---- .../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 6 ++---- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +---- arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +---- arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +---- .../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 6 ++---- .../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 6 ++---- .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 6 ++---- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 5 +---- .../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 6 ++---- 12 files changed, 36 insertions(+), 44 deletions(-) create mode 100644 arch/arm/dts/socfpga-common-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi new file mode 100644 index 0000000000..322c858c4b --- /dev/null +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (c) 2019 Simon Goldschmidt + */ +/{ + soc { + u-boot,dm-pre-reloc; + }; +}; + +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi index c44d1ee2fa..e059831a08 100644 --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index a387071674..6439daa525 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "Devboards.de DBM-SoC1"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi index 08d81da169..0219c6948d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -6,14 +6,12 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index e9105743ea..b620dd8dda 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -6,6 +6,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "Terasic DE10-Nano"; @@ -26,10 +27,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index 4f076bce93..ff1e61e0cb 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "Terasic DE1-SoC"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index b7054bfd5a..1788e4dfa3 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "SoCFPGA Cyclone V IS1"; @@ -31,10 +32,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 9436e0fa8b..3b6887fb84 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&can0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi index 648f1bd01d..7c569488e6 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi index 31bd1dba0f..ad88d3ff7b 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 6a6c29be79..26efe04de0 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "SoCFPGA Cyclone V SR1500"; @@ -27,10 +28,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 360b946ba2..743ad3a5c0 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb0; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 {