From: Lokesh Vutla lokeshvutla@ti.com
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD registers. In EMIF_PHY_CTRL: Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the read latency expected will be CL+3 as per tests from HW folks. Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug purpose. With out this resume is not working(Still waiting for PHY team to come back for better explanation).
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am43xx/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 0c9f0ef..7a28063 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -206,7 +206,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E084008, + .emif_ddr_phy_ctlr_1 = 0x0E004008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00400040, .emif_ddr_ext_phy_ctrl_3 = 0x00400040,