Re: [U-Boot] [PATCH v2 37/56] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

On 26 July 2017 at 04:40, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:

To implement a TPL stage (incl. its DRAM controller setup) for the RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL configuration details for the common DRAM operating speeds found on RK3368 boards.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Changes in v2: None

drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)

Reviewed-by: Simon Glass sjg@chromium.org