On Tue, Jan 28, 2020 at 2:41 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: 27 January 2020 13:22 To: Pragnesh Patel pragnesh.patel@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Atish Patra atish.patra@wdc.com; palmerdabbelt@google.com; Bin Meng bmeng.cn@gmail.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Troy Benjegerdes ( Sifive) troy.benjegerdes@sifive.com; Anup Patel anup.patel@wdc.com; Sagar Kadam sagar.kadam@sifive.com Subject: Re: [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel pragnesh.patel@sifive.com wrote:
Add ddr4 controller and phy related files
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com
board/sifive/fu540/Makefile | 4 + board/sifive/fu540/ddr.c | 868 ++++++++++++++++++++ board/sifive/fu540/regconfig-ctl.h | 270 ++++++ board/sifive/fu540/regconfig-phy.h | 1220
++++++++++++++++++++++++++++
board/sifive/fu540/ux00ddr.h | 45 + 5 files changed, 2407 insertions(+) create mode 100644 board/sifive/fu540/ddr.c create mode 100644 board/sifive/fu540/regconfig-ctl.h create mode 100644 board/sifive/fu540/regconfig-phy.h create mode 100644 board/sifive/fu540/ux00ddr.h
[snip]
Sorry, this entire ddr code look very difficult to undestand or review. I understand it is driven from the vendor blog or so but it is not in proper shape to mege it on mainline, IMHO. But I'm sure if we have a close attenetion then it would definetly a ready peice for mainline and readable for future proof.
Suggestions would be try to differentiate the code into driver and timings, so we can write drivers/ram and the timings would be some sort of dtsi or script or platdata would centainly ddr chip depenent.
I agree with Jagan. And if we don't write RAM drivers, perhaps we need put these codes into arch/riscv/cpu/sifive for the memory controller is SoC specific stuff.
I can help here, based on my experince with rockchip ddr, if you need any?
@Anup Patel do you have any comment on this?
Regards, Bin