-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Friday, February 05, 2010 12:12 PM To: Gupta, Ajay Kumar Cc: Neal Tew; u-boot@lists.denx.de Subject: Re: [U-Boot] TI Davinci and MUSB
Dear "Gupta, Ajay Kumar",
In message 19F8576C6E063C45BE387C64729E7394044A776008@dbde02.ent.ti.com you wrote:
Opps, there are actually 32 intermediate register each of 32 bits.
So the correct one is as Neal suggested.
- u32 reserved[0x20];
- u32 reserved[020/4];
0x20 / 4 = 8
020 / 4 = 4
It was typing mistake...
Thanks, Ajay
Best regards,
Wolfgang Denk
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