To get more exactly sclk value, used the get_mmc_clk.
Signed-off-by: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 78 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 79 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 2f7048b..90fa45c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -360,6 +360,44 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; }
+/* exynos4: return mmc clock frequency */ +static unsigned long exynos4_get_mmc_clk(int dev_index) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + if (dev_index == 0) { + ratio = readl(&clk->div_fsys0); + pre_ratio = readl(&clk->div_fsys0); + } else if (dev_index == 4) { + ratio = readl(&clk->div_fsys3); + pre_ratio = readl(&clk->div_fsys3); + } else + return 0; + + ratio = ratio & 0xf; + pre_ratio = (pre_ratio >> (dev_index + 8)) & 0xff; + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -387,6 +425,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); }
+/* exynos5: return mmc clock frequency */ +static unsigned long exynos5_get_mmc_clk(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + ratio = readl(&clk->div_fsys1); + ratio = (ratio >> (dev_index << 2)) & 0xf; + pre_ratio = readl(&clk->div_fsys1); + pre_ratio = (pre_ratio >> ((dev_index<< 4) + 8)) & 0xff; + + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos5: set the mmc clock */ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) { @@ -446,6 +516,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); }
+unsigned long get_mmc_clk(int dev_index) +{ + if (cpu_is_exynos5()) + return exynos5_get_mmc_clk(dev_index); + else + return exynos4_get_mmc_clk(dev_index); +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ff0f641..9e9d390 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -31,6 +31,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); +unsigned long get_mmc_clk(int dev_index); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);