8 Jan
2015
8 Jan
'15
7:21 a.m.
On Tuesday 23 December 2014 03:56 AM, Felipe Balbi wrote:
From: James Doublesin doublesin@ti.com
Need to provide PLL values for all possible input frequencies (19.2, 24, 25, 26MHz). Values provide are also optimized for jitter (needed especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com
Tested the full series.
Tested-by: Mugunthan V N mugunthanvnm@ti.com
Regards Mugunthan V N