EELADR - 0XF4010000, it is INIT_RAM address, why the transaction with address(0xF4010000) go to system bus? It should keep in the cache due to cache lock, never out to system bus.
I don't know why... and it just happened.... shall I allocate a entry of tlb for it?? or cover it in some space ?
Why the PCIE1_IO have 32G space? It seems like one typo.
I reduce the size of PCIE1_IO and it doesn't help.
The u-boot version is very old, if you can post your start.S and board.h,It
will be helpful.
Thanks, Dave
I didn't change anything in start.s and I build it from the latest LTIB of mpc8544 of freescale. But I did change memory map in board.h.
include/configs/mpc8544ds.h is as below: ============================================================================== /* * mpc8544ds board configuration file * */ #ifndef __CONFIG_H #define __CONFIG_H
/* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8544 1 #define CONFIG_MPC8544DS 1
#define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller 1 */ #define CONFIG_PCIE1 0 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 0 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE3 0 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_DLL #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD #undef CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/* * When initializing flash, if we cannot find the manufacturer ID, * assume this is the AMD flash associated with the CDS board. * This allows booting from a promjet. */ #define CONFIG_ASSUME_AMD_FLASH
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
#ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
/* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #undef CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/* * Only possible on E500 Version 2 or newer cores. */ #define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 #define CFG_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */
/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
/* * DDR Setup */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
/* * Make sure required options are set */ #ifndef CONFIG_SPD_EEPROM #error ("CONFIG_SPD_EEPROM is required") #endif
#undef CONFIG_CLOCKS_IN_MHZ
/* * Memory map * * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable * * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable * * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable * * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable * * Localbus cacheable * * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 * * Localbus non-cacheable * * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable * */ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1
#define CFG_ID_EEPROM #define ID_EEPROM_ADDR 0x57
/* * Local Bus Definitions */ #define CFG_BOOT_BLOCK 0xffc00000 /* boot TLB */ #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ #define CFG_FLASH_BASE 0xffc00000 /* start of FLASH 4M */
#define CFG_BR0_PRELIM 0xffc01001 #define CFG_BR1_PRELIM 0xff000881
#define CFG_OR0_PRELIM 0xffc06e65 /*NAND Flash 1*/ #define CFG_OR1_PRELIM 0xfffe6000
#define CFG_BR3_PRELIM 0xff040881 /*NAND Flash 2*/ #define CFG_OR3_PRELIM 0xfffe6000
//#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE}
#define CFG_FLASH_QUIET_TEST #define CFG_MAX_FLASH_BANKS 3 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO /* #define CFG_FLASH_AMD_CHECK_DQ7 */ #define CFG_FLASH_AMD_CHECK_DATA_COMPARE
#define CFG_LBC_NONCACHE_BASE 0xf8000000
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch * register */ #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ #define PIXIS_VCTL 0x10 /* VELA Control Register */ #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM 1 #define CFG_INIT_L1_LOCK 1 #define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ #define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */
/* define to use L2SRAM as initial stack */ #undef CONFIG_L2_INIT_RAM #define CFG_INIT_L2_ADDR 0xf8fc0000 #define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */
#ifdef CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR #define CFG_INIT_RAM_END CFG_INIT_L1_END #else #define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR #define CFG_INIT_RAM_END CFG_INIT_L2_END #endif
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif
/* pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8544@0" #define OF_SOC "soc8544@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
/* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3100
/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
#define CFG_PCI1_MEM_BASE 0xc0000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe1000000 #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
/* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 #define CFG_PCI_MEMORY_PHYS 0x00000000 #define CFG_PCI_MEMORY_SIZE 0x80000000
/* controller 2, Slot 1, tgtid 1, Base address a000 */ #define CFG_PCIE2_MEM_BASE 0x0 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCIE2_IO_BASE 0x00000000 #define CFG_PCIE2_IO_PHYS 0x0 #define CFG_PCIE2_IO_SIZE 0x00000000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address 8000 */ #define CFG_PCIE1_MEM_BASE 0x0 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCIE1_IO_BASE 0x00000000 #define CFG_PCIE1_IO_PHYS 0x0 #define CFG_PCIE1_IO_SIZE 0x00000000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */ #define CFG_PCIE3_MEM_BASE 0xb0000000 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE #define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CFG_PCIE3_IO_BASE 0x00000000 #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CFG_PCIE3_IO_SIZE 0x00000000 /* 1M */ #define CFG_PCIE3_MEM_BASE2 0x0 #define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 #define CFG_PCIE3_MEM_SIZE2 0x00000000 /* 1M */
#if defined(CONFIG_PCI)
/* video */ #define CONFIG_VIDEO
#if defined(CONFIG_VIDEO) #define VIDEO_IO_OFFSET CFG_PCIE1_IO_PHYS #define CONFIG_BIOSEMU #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/ #define CFG_ISA_IO_BASE_ADDRESS CFG_PCIE1_IO_PHYS #endif
#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #define CONFIG_RTL8139
#ifdef CONFIG_RTL8139 /* This macro is used by RTL8139 but not defined in PPC architecture */ #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 #endif
#ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI #define CONFIG_SATA_ULI5288 #define CFG_SCSI_MAX_SCSI_ID 4 #define CFG_SCSI_MAX_LUN 1 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif /* SCSCI */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif
#define CONFIG_SGMII_RISER #define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c #define CONFIG_TSEC_TBI #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0 #define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */
/* * Environment */ #define CFG_ENV_IS_IN_FLASH 1 #if CFG_MONITOR_BASE > 0xfff80000 #define CFG_ENV_ADDR 0xfff80000 #else #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) #endif #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
/* * Command line configuration. */ #include <config_cmd_default.h>
#define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII
#if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_NET #define CONFIG_CMD_SCSI #define CONFIG_CMD_EXT2 #endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif
/* * Internal Definitions * * Boot Flags */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif
/* * Environment Configuration */
/* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD #define CONFIG_HAS_ETH3 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif
#define CONFIG_IPADDR 192.168.1.251
#define CONFIG_HOSTNAME 8544ds_unknown #define CONFIG_ROOTPATH /nfs/mpc85xx #define CONFIG_BOOTFILE 8544ds/uImage.uboot #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1 #define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_NETMASK 255.255.0.0
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) #define PCIE_ENV \ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ "pcieerr=md ${a}020 1; md ${a}e00 e;" \ "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ "pci d.w $b.0 56 1;" \ "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ "pci w $b.0 130 ffffffff\0" \ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ "pcie1regs=setenv a e000a; run pciereg\0" \ "pcie2regs=setenv a e0009; run pciereg\0" \ "pcie3regs=setenv a e000b; run pciereg\0" \ "pcie1cfg=setenv b 3; run pciecfg\0" \ "pcie2cfg=setenv b 5; run pciecfg\0" \ "pcie3cfg=setenv b 0; run pciecfg\0" \ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \ "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \ "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \ "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0" #else #define PCIE_ENV "" #endif
#if defined(CONFIG_PCI1) #define PCI_ENV \ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ "echo e;md ${a}e00 9\0" \ "pci1regs=setenv a e0008; run pcireg\0" \ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ "pci d.w $b.0 56 1\0" \ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \ "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \ "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0" #else #define PCI_ENV "" #endif
#if defined(CONFIG_TSEC_ENET) #define ENET_ENV \ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ "md ${a}098 2\0" \ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ "echo mib;md ${a}680 31\0" \ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ "enet1regs=setenv a e0024; run enetreg\0" \ "enet3regs=setenv a e0026; run enetreg\0" #else #define ENET_ENV "" #endif
#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ "erase " MK_STR(TEXT_BASE) " +$filesize; " \ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8544ds/ramdisk.uboot\0" \ "dtbaddr=c00000\0" \ "dtbfile=8544ds/mpc8544ds.dtb\0" \ "bdev=sda3\0" \ "eoi=mw e00400b0 0\0" \ "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ "ddrregs=setenv a e0002; run ddrreg\0" \ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ "guregs=setenv a e00e0; run gureg\0" \ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ "ecmregs=setenv a e0001; run ecmreg\0" \ "lawregs=md e0000c08 4b\0" \ "lbcregs=md e0005000 36\0" \ "dma0regs=md e0021100 12\0" \ "dma1regs=md e0021180 12\0" \ "dma2regs=md e0021200 12\0" \ "dma3regs=md e0021280 12\0" \ PCIE_ENV \ PCI_ENV \ ENET_ENV
#define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $dtbaddr $dtbfile;" \ "bootm $loadaddr - $dtbaddr"
#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ "tftp $dtbaddr $dtbfile;" \ "bootm $loadaddr $ramdiskaddr $dtbaddr"
#define CONFIG_BOOTCOMMAND \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $dtbaddr $dtbfile;" \ "bootm $loadaddr - $dtbaddr"
#endif /* __CONFIG_H */ =============================================================================
the cpu/mpc85xx/start.s is as below: ============================================================================ /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards * * The processor starts at 0xfffffffc and the code is first executed in the * last 4K page(0xfffff000-0xffffffff) in flash/rom. * */
#include <config.h> #include <mpc85xx.h> #include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl> #include <ppc_defs.h>
#include <asm/cache.h> #include <asm/mmu.h>
#ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif
#undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
/* * Set up GOT: Global Offset Table * * Use r14 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end) GOT_ENTRY(_end) GOT_ENTRY(__bss_start) END_GOT
/* * e500 Startup -- after reset only the last 4KB of the effective * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg * section is located at THIS LAST page and basically does three * things: clear some registers, set up exception tables and * add more TLB entries for 'larger spaces'(e.g. the boot rom) to * continue the boot procedure.
* Once the boot rom is mapped by TLB entries we can proceed * with normal startup. * */
.section .bootpg,"ax" .globl _start_e500
_start_e500:
/* clear registers/arrays not reset by hardware */
/* L1 */ li r0,2 mtspr L1CSR0,r0 /* invalidate d-cache */ mtspr L1CSR1,r0 /* invalidate i-cache */
mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */
/* * Enable L1 Caches early * */
lis r2,L1CSR0_CPE@H /* enable parity */ ori r2,r2,L1CSR0_DCE mtspr L1CSR0,r2 /* enable L1 Dcache */ isync mtspr L1CSR1,r2 /* enable L1 Icache */ isync msync
/* Setup interrupt vectors */ lis r1,TEXT_BASE@h mtspr IVPR,r1
li r1,0x0100 mtspr IVOR0,r1 /* 0: Critical input */ li r1,0x0200 mtspr IVOR1,r1 /* 1: Machine check */ li r1,0x0300 mtspr IVOR2,r1 /* 2: Data storage */ li r1,0x0400 mtspr IVOR3,r1 /* 3: Instruction storage */ li r1,0x0500 mtspr IVOR4,r1 /* 4: External interrupt */ li r1,0x0600 mtspr IVOR5,r1 /* 5: Alignment */ li r1,0x0700 mtspr IVOR6,r1 /* 6: Program check */ li r1,0x0800 mtspr IVOR7,r1 /* 7: floating point unavailable */ li r1,0x0900 mtspr IVOR8,r1 /* 8: System call */ /* 9: Auxiliary processor unavailable(unsupported) */ li r1,0x0a00 mtspr IVOR10,r1 /* 10: Decrementer */ li r1,0x0b00 mtspr IVOR11,r1 /* 11: Interval timer */ li r1,0x0c00 mtspr IVOR12,r1 /* 12: Watchdog timer */ li r1,0x0d00 mtspr IVOR13,r1 /* 13: Data TLB error */ li r1,0x0e00 mtspr IVOR14,r1 /* 14: Instruction TLB error */ li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */
/* * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB * region before we can access any CCSR registers such as L2 * registers, Local Access Registers,etc. We will also re-allocate * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup. * * Please refer to board-specif directory for TLB1 entry configuration. * (e.g. board/<yourboard>/init.S) * */ bl tlb1_entry mr r5,r0 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ mtctr r4
0: lwzu r6,4(r5) lwzu r7,4(r5) lwzu r8,4(r5) lwzu r9,4(r5) mtspr MAS0,r6 mtspr MAS1,r7 mtspr MAS2,r8 mtspr MAS3,r9 isync msync tlbwe isync bdnz 0b
1: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* Special sequence needed to update CCSRBAR itself */ lis r4,CFG_CCSRBAR_DEFAULT@h ori r4,r4,CFG_CCSRBAR_DEFAULT@l
lis r5,CFG_CCSRBAR@h ori r5,r5,CFG_CCSRBAR@l srwi r6,r5,12 stw r6,0(r4) isync
lis r5,0xffff ori r5,r5,0xf000 lwz r5,0(r5) isync
lis r3,CFG_CCSRBAR@h lwz r5,CFG_CCSRBAR@l(r3) isync #endif
/* set up local access windows, defined at board/<boardname>/init.S */ lis r7,CFG_CCSRBAR@h ori r7,r7,CFG_CCSRBAR@l
bl law_entry mr r6,r0 lwzu r5,0(r6) /* how many windows we actually use */ mtctr r5
li r2,0x0c28 /* the first pair is reserved for */ li r1,0x0c30 /* boot-over-rio-or-pci */
0: lwzu r4,4(r6) lwzu r3,4(r6) stwx r4,r7,r2 stwx r3,r7,r1 addi r2,r2,0x0020 addi r1,r1,0x0020 bdnz 0b
/* Clear and set up some registers. */ li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ mttbl r0 /* prevent fit & wdt exceptions */ mttbu r0 mtspr TSR,r1 /* clear all timer exception status */ mtspr TCR,r0 /* disable all */ mtspr ESR,r0 /* clear exception syndrome register */ mtspr MCSR,r0 /* machine check syndrome register */ mtxer r0 /* clear integer exception register */ lis r1,0x0002 /* set CE bit (Critical Exceptions) */ ori r1,r1,0x1200 /* set ME/DE bit */ mtmsr r1 /* change MSR */ isync
/* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ #if defined(CONFIG_ENABLE_36BIT_PHYS) ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */ #else ori r0,r0,HID0_TBEN@l /* enable Timebase */ #endif mtspr HID0,r0
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0
/* Enable Branch Prediction */ #if defined(CONFIG_BTB) li r0,0x201 /* BBFI = 1, BPEN = 1 */ mtspr BUCSR,r0 #endif
#if defined(CFG_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ ori r0,r0,CFG_INIT_DBCR@l mtspr DBCR0,r0 #endif
/* L1 DCache is used for initial RAM */
/* Allocate Initial RAM in data cache. */ lis r3,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l li r2,512 /* 512*32=16K */ mtctr r2 li r0,0 1: dcbz r0,r3 dcbtls 0,r0,r3 addi r3,r3,32 bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */ #ifdef CFG_RAMBOOT bl 3f b _start_cont #else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ lis r3,CFG_MONITOR_BASE@h ori r3,r3,CFG_MONITOR_BASE@l addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 #endif
3: li r0,0 #if !defined(CONFIG_CW) mtspr SRR1,r0 /* Keep things disabled for now */ #endif mflr r1 mtspr SRR0,r1 rfi isync
.text .globl _start _start: .long 0x27051956 /* U-BOOT Magic Number */ .globl version_string version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0"
.align 4 .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r1,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET@l
li r0,0 stwu r0,-4(r1) stwu r0,-4(r1) /* Terminate call chain */
stwu r1,-8(r1) /* Save back chain and move SP */ lis r0,RESET_VECTOR@h /* Address of reset vector */ ori r0,r0,RESET_VECTOR@l stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT bl cpu_init_f bl board_init_f isync
. = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors:
/* Critical input. */ CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
/* Machine check */ MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */ STD_EXCEPTION(0x0300, DataStorage, UnknownException)
/* Instruction Storage exception. */ STD_EXCEPTION(0x0400, InstStorage, UnknownException)
/* External Interrupt exception. */ STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
/* Alignment exception. */ . = 0x0600 Alignment: EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ lwz r6,GOT(transfer_to_handler) mtlr r6 blrl .L_Alignment: .long AlignmentException - _start + _START_OFFSET .long int_return - _start + _START_OFFSET
/* Program check exception */ . = 0x0700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ lwz r6,GOT(transfer_to_handler) mtlr r6 blrl .L_ProgramCheck: .long ProgramCheckException - _start + _START_OFFSET .long int_return - _start + _START_OFFSET
/* No FPU on MPC85xx. This exception is not supposed to happen. */ STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
. = 0x0900 /* * r0 - SYSCALL number * r3-... arguments */ SystemCall: addis r11,r0,0 /* get functions table addr */ ori r11,r11,0 /* Note: this code is patched in trap_init */ addis r12,r0,0 /* get number of functions */ ori r12,r12,0
cmplw 0,r0,r12 bge 1f
rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ add r11,r11,r0 lwz r11,0(r11)
li r20,0xd00-4 /* Get stack pointer */ lwz r12,0(r20) subi r12,r12,12 /* Adjust stack pointer */ li r0,0xc00+_end_back-SystemCall cmplw 0,r0,r12 /* Check stack overflow */ bgt 1f stw r12,0(r20)
mflr r0 stw r0,0(r12) mfspr r0,SRR0 stw r0,4(r12) mfspr r0,SRR1 stw r0,8(r12)
li r12,0xc00+_back-SystemCall mtlr r12 mtspr SRR0,r11
1: SYNC rfi _back:
mfmsr r11 /* Disable interrupts */ li r12,0 ori r12,r12,MSR_EE andc r11,r11,r12 SYNC /* Some chip revs need this... */ mtmsr r11 SYNC
li r12,0xd00-4 /* restore regs */ lwz r12,0(r12)
lwz r11,0(r12) mtlr r11 lwz r11,4(r12) mtspr SRR0,r11 lwz r11,8(r12) mtspr SRR1,r11
addi r12,r12,12 /* Adjust stack pointer */ li r20,0xd00-4 stw r12,0(r20)
SYNC rfi _end_back:
STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
.globl _end_of_vectors _end_of_vectors:
. = . + (0x100 - ( . & 0xff )) /* align for debug */
/* * This code finishes saving the registers to the exception frame * and jumps to the appropriate handler for the exception. * Register r21 is pointer into trap frame, r1 has new stack pointer. */ .globl transfer_to_handler transfer_to_handler: stw r22,_NIP(r21) lis r22,MSR_POW@h andc r23,r23,r22 stw r23,_MSR(r21) SAVE_GPR(7, r21) SAVE_4GPRS(8, r21) SAVE_8GPRS(12, r21) SAVE_8GPRS(24, r21)
mflr r23 andi. r24,r23,0x3f00 /* get vector offset */ stw r24,TRAP(r21) li r22,0 stw r22,RESULT(r21) mtspr SPRG2,r22 /* r1 is now kernel sp */
lwz r24,0(r23) /* virtual address of handler */ lwz r23,4(r23) /* where to go when done */ mtspr SRR0,r24 mtspr SRR1,r20 mtlr r23 SYNC rfi /* jump to handler, enable MMU */
int_return: mfmsr r28 /* Disable interrupts */ li r4,0 ori r4,r4,MSR_EE andc r28,r28,r4 SYNC /* Some chip revs need this... */ mtmsr r28 SYNC lwz r2,_CTR(r1) lwz r0,_LINK(r1) mtctr r2 mtlr r0 lwz r2,_XER(r1) lwz r0,_CCR(r1) mtspr XER,r2 mtcrf 0xFF,r0 REST_10GPRS(3, r1) REST_10GPRS(13, r1) REST_8GPRS(23, r1) REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) mtspr SRR0,r2 mtspr SRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfi
crit_return: mfmsr r28 /* Disable interrupts */ li r4,0 ori r4,r4,MSR_EE andc r28,r28,r4 SYNC /* Some chip revs need this... */ mtmsr r28 SYNC lwz r2,_CTR(r1) lwz r0,_LINK(r1) mtctr r2 mtlr r0 lwz r2,_XER(r1) lwz r0,_CCR(r1) mtspr XER,r2 mtcrf 0xFF,r0 REST_10GPRS(3, r1) REST_10GPRS(13, r1) REST_8GPRS(23, r1) REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) mtspr SPRN_CSRR0,r2 mtspr SPRN_CSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfci
mck_return: mfmsr r28 /* Disable interrupts */ li r4,0 ori r4,r4,MSR_EE andc r28,r28,r4 SYNC /* Some chip revs need this... */ mtmsr r28 SYNC lwz r2,_CTR(r1) lwz r0,_LINK(r1) mtctr r2 mtlr r0 lwz r2,_XER(r1) lwz r0,_CCR(r1) mtspr XER,r2 mtcrf 0xFF,r0 REST_10GPRS(3, r1) REST_10GPRS(13, r1) REST_8GPRS(23, r1) REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) mtspr SPRN_MCSRR0,r2 mtspr SPRN_MCSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfmci
/* Cache functions. */ invalidate_icache: mfspr r0,L1CSR1 ori r0,r0,L1CSR1_ICFI msync isync mtspr L1CSR1,r0 isync blr /* entire I cache */
invalidate_dcache: mfspr r0,L1CSR0 ori r0,r0,L1CSR0_DCFI msync isync mtspr L1CSR0,r0 isync blr
.globl icache_enable icache_enable: mflr r8 bl invalidate_icache mtlr r8 isync mfspr r4,L1CSR1 ori r4,r4,0x0001 oris r4,r4,0x0001 mtspr L1CSR1,r4 isync blr
.globl icache_disable icache_disable: mfspr r0,L1CSR1 lis r3,0 ori r3,r3,L1CSR1_ICE andc r0,r0,r3 mtspr L1CSR1,r0 isync blr
.globl icache_status icache_status: mfspr r3,L1CSR1 andi. r3,r3,L1CSR1_ICE blr
.globl dcache_enable dcache_enable: mflr r8 bl invalidate_dcache mtlr r8 isync mfspr r0,L1CSR0 ori r0,r0,0x0001 oris r0,r0,0x0001 msync isync mtspr L1CSR0,r0 isync blr
.globl dcache_disable dcache_disable: mfspr r3,L1CSR0 lis r4,0 ori r4,r4,L1CSR0_DCE andc r3,r3,r4 mtspr L1CSR0,r0 isync blr
.globl dcache_status dcache_status: mfspr r3,L1CSR0 andi. r3,r3,L1CSR0_DCE blr
.globl get_pir get_pir: mfspr r3,PIR blr
.globl get_pvr get_pvr: mfspr r3,PVR blr
.globl get_svr get_svr: mfspr r3,SVR blr
.globl wr_tcr wr_tcr: mtspr TCR,r3 blr
/*------------------------------------------------------------------------------- */ /* Function: in8 */ /* Description: Input 8 bits */ /*------------------------------------------------------------------------------- */ .globl in8 in8: lbz r3,0x0000(r3) blr
/*------------------------------------------------------------------------------- */ /* Function: out8 */ /* Description: Output 8 bits */ /*------------------------------------------------------------------------------- */ .globl out8 out8: stb r4,0x0000(r3) blr
/*------------------------------------------------------------------------------- */ /* Function: out16 */ /* Description: Output 16 bits */ /*------------------------------------------------------------------------------- */ .globl out16 out16: sth r4,0x0000(r3) blr
/*------------------------------------------------------------------------------- */ /* Function: out16r */ /* Description: Byte reverse and output 16 bits */ /*------------------------------------------------------------------------------- */ .globl out16r out16r: sthbrx r4,r0,r3 blr
/*------------------------------------------------------------------------------- */ /* Function: out32 */ /* Description: Output 32 bits */ /*------------------------------------------------------------------------------- */ .globl out32 out32: stw r4,0x0000(r3) blr
/*------------------------------------------------------------------------------- */ /* Function: out32r */ /* Description: Byte reverse and output 32 bits */ /*------------------------------------------------------------------------------- */ .globl out32r out32r: stwbrx r4,r0,r3 blr
/*------------------------------------------------------------------------------- */ /* Function: in16 */ /* Description: Input 16 bits */ /*------------------------------------------------------------------------------- */ .globl in16 in16: lhz r3,0x0000(r3) sync blr
/*------------------------------------------------------------------------------- */ /* Function: in16r */ /* Description: Input 16 bits and byte reverse */ /*------------------------------------------------------------------------------- */ .globl in16r in16r: lhbrx r3,r0,r3 sync blr
/*------------------------------------------------------------------------------- */ /* Function: in32 */ /* Description: Input 32 bits */ /*------------------------------------------------------------------------------- */ .globl in32 in32: lwz 3,0x0000(3) sync blr
/*------------------------------------------------------------------------------- */ /* Function: in32r */ /* Description: Input 32 bits and byte reverse */ /*------------------------------------------------------------------------------- */ .globl in32r in32r: lwbrx r3,r0,r3 sync blr
/*------------------------------------------------------------------------------- */ /* Function: ppcDcbf */ /* Description: Data Cache block flush */ /* Input: r3 = effective address */ /* Output: none. */ /*------------------------------------------------------------------------------- */ .globl ppcDcbf ppcDcbf: dcbf r0,r3 blr
/*------------------------------------------------------------------------------- */ /* Function: ppcDcbi */ /* Description: Data Cache block Invalidate */ /* Input: r3 = effective address */ /* Output: none. */ /*------------------------------------------------------------------------------- */ .globl ppcDcbi ppcDcbi: dcbi r0,r3 blr
/*-------------------------------------------------------------------------- * Function: ppcDcbz * Description: Data Cache block zero. * Input: r3 = effective address * Output: none. *-------------------------------------------------------------------------- */
.globl ppcDcbz ppcDcbz: dcbz r0,r3 blr
/*------------------------------------------------------------------------------- */ /* Function: ppcSync */ /* Description: Processor Synchronize */ /* Input: none. */ /* Output: none. */ /*------------------------------------------------------------------------------- */ .globl ppcSync ppcSync: sync blr
/*------------------------------------------------------------------------------*/
/* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * * r3 = dest * r4 = src * r5 = length in bytes * r6 = cachelinesize */ .globl relocate_code relocate_code: mr r1,r3 /* Set new stack pointer */ mr r9,r4 /* Save copy of Init Data pointer */ mr r10,r5 /* Save copy of Destination Address */
mr r3,r5 /* Destination Address */ lis r4,CFG_MONITOR_BASE@h /* Source Address */ ori r4,r4,CFG_MONITOR_BASE@l lwz r5,GOT(__init_end) sub r5,r5,r4 li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
/* * Fix GOT pointer: * * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address * * Offset: */ sub r15,r10,r4
/* First our own GOT */ add r14,r14,r15 /* the the one used by the C code */ add r30,r30,r15
/* * Now relocate code */
cmplw cr1,r3,r4 addi r0,r5,3 srwi. r0,r0,2 beq cr1,4f /* In place copy is not necessary */ beq 7f /* Protect against 0 count */ mtctr r0 bge cr1,2f
la r8,-4(r4) la r7,-4(r3) 1: lwzu r0,4(r8) stwu r0,4(r7) bdnz 1b b 4f
2: slwi r0,r0,2 add r8,r4,r0 add r7,r3,r0 3: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b
/* * Now flush the cache: note that we must start from a cache aligned * address. Otherwise we might miss one cache line. */ 4: cmpwi r6,0 add r5,r3,r5 beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 mr r4,r3 5: dcbst 0,r4 add r4,r4,r6 cmplw r4,r5 blt 5b sync /* Wait for all dcbst to complete on bus */ mr r4,r3 6: icbi 0,r4 add r4,r4,r6 cmplw r4,r5 blt 6b 7: sync /* Wait for all icbi to complete on bus */ isync
/* * Re-point the IVPR at RAM */ mtspr IVPR,r10
/* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */
addi r0,r10,in_ram - _start + _START_OFFSET mtlr r0 blr /* NEVER RETURNS! */ .globl in_ram in_ram:
/* * Relocation Function, r14 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. */ li r0,__got2_entries@sectoff@l la r3,GOT(_GOT2_TABLE_) lwz r11,GOT(_GOT2_TABLE_) mtctr r0 sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) add r0,r0,r11 stw r0,0(r3) bdnz 1b
/* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ 2: li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 addi r3,r3,-4 beq 4f 3: lwzu r4,4(r3) lwzux r0,r4,r11 add r0,r0,r11 stw r10,0(r3) stw r0,0(r4) bdnz 3b 4: clear_bss: /* * Now clear BSS segment */ lwz r3,GOT(__bss_start) lwz r4,GOT(_end)
cmplw 0,r3,r4 beq 6f
li r0,0 5: stw r0,0(r3) addi r3,r3,4 cmplw 0,r3,r4 bne 5b 6:
mr r3,r9 /* Init Data pointer */ mr r4,r10 /* Destination Address */ bl board_init_r
/* * Copy exception vector code to low memory * * r3: dest_addr * r7: source address, r8: end address, r9: target address */ .globl trap_init trap_init: lwz r7,GOT(_start_of_vectors) lwz r8,GOT(_end_of_vectors)
li r9,0x100 /* reset vector always at 0x100 */
cmplw 0,r7,r8 bgelr /* return if r7>=r8 - just in case */
mflr r4 /* save link register */ 1: lwz r0,0(r7) stw r0,0(r9) addi r7,r7,4 addi r9,r9,4 cmplw 0,r7,r8 bne 1b
/* * relocate `hdlr' and `int_return' entries */ li r7,.L_CriticalInput - _start + _START_OFFSET bl trap_reloc li r7,.L_MachineCheck - _start + _START_OFFSET bl trap_reloc li r7,.L_DataStorage - _start + _START_OFFSET bl trap_reloc li r7,.L_InstStorage - _start + _START_OFFSET bl trap_reloc li r7,.L_ExtInterrupt - _start + _START_OFFSET bl trap_reloc li r7,.L_Alignment - _start + _START_OFFSET bl trap_reloc li r7,.L_ProgramCheck - _start + _START_OFFSET bl trap_reloc li r7,.L_FPUnavailable - _start + _START_OFFSET bl trap_reloc li r7,.L_Decrementer - _start + _START_OFFSET bl trap_reloc li r7,.L_IntervalTimer - _start + _START_OFFSET li r8,_end_of_vectors - _start + _START_OFFSET 2: bl trap_reloc addi r7,r7,0x100 /* next exception vector */ cmplw 0,r7,r8 blt 2b
lis r7,0x0 mtspr IVPR,r7
mtlr r4 /* restore link register */ blr
/* * Function: relocate entries for one exception vector */ trap_reloc: lwz r0,0(r7) /* hdlr ... */ add r0,r0,r3 /* ... += dest_addr */ stw r0,0(r7)
lwz r0,4(r7) /* int_return ... */ add r0,r0,r3 /* ... += dest_addr */ stw r0,4(r7)
blr
#ifdef CFG_INIT_RAM_LOCK .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3,(CFG_INIT_RAM_ADDR & ~31)@h ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l li r4,512 mtctr r4 1: icbi r0,r3 dcbi r0,r3 addi r3,r3,32 bdnz 1b sync /* Wait for all icbi to complete on bus */ isync blr #endif ============================================================================
A quick question is, there is a FPGA(actel pixis) in mpc8544ds board, and it seems related with system clock ??? There is no such FPGA in my board, is it the problem??
Shall I remove the pixis related code from board.h and board.c and try to configure system clock by myself ?? Still confusing.....
Thanks for any help.
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