On 08/01/2018 05:42 PM, Simon Goldschmidt wrote:
Marek Vasut <marex@denx.de mailto:marex@denx.de> schrieb am Mi., 1. Aug. 2018, 09:35:
On 08/01/2018 09:29 AM, Goldschmidt Simon wrote: > > On 30.07.2018 16:04, Marek Vasut wrote: >> On 07/30/2018 04:03 PM, Simon Goldschmidt wrote: >>> >>> On 12.05.2018 22:28, Marek Vasut wrote: >>>> Pull the serial port configuration from DT and use DM serial instead >>>> of having the serial configuration in two places, DT and board config. [..]While debugging, a more generic question: which drivers are now remaining non-DM for socfpga?
Not much I believe, I can't think of anything right now.
And am I correct with the assumption that we could get rid of the qts files (other than sdram maybe) by implementing pinctrl and clk drivers as DM drivers? (Not that I would have found documentation about the pin mux hardware cyclone5...)
Yes. The pinmux docs are probably not public, it has to do with the iocsr ring programming and that's super-secret for whatever reason. What Altera did on Arria10 is pure trash, they encode registers in DT and are done with it. If you can design something saner, that'd be so nice.
I am working on a clock driver for Arria10 now, I might do Gen5 too afterward, since the clock block is similar. The clock DT bindings on the other hand are complete insanity, words fail me. The clock stuff in U-Boot on SoCFPGA right now is a complete disaster too, the way stuff gets added to mach-socfpga is really irritating.
I'm looking for a way to control pins from a fit image that includes kernel, dts and fpga because the pins may change depending on the fpga config...
DTOs maybe ?
Simon (from my private mail)