-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Tuesday, December 22, 2020 12:50 AM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v5 10/18] net: designware: socfpga: Add ATF support for MAC driver
From: Chee Hong Ang chee.hong.ang@intel.com
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com
v5
Call secure register access helper function to write the secure register. Return error if fail to write the PHY related secure register.
drivers/net/dwmac_socfpga.c | 38 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index e93561dffa..8efb88c8fb 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -6,6 +6,8 @@ */
#include <common.h> +#include <asm/arch/secure_reg_helper.h> #include +<asm/arch/system_manager.h> #include <asm/io.h> #include <dm.h> #include <clk.h> @@ -17,8 +19,6 @@ #include <dm/device_compat.h> #include <linux/err.h>
-#include <asm/arch/system_manager.h>
struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; void *phy_intf; @@ -64,6 +64,33 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); }
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) {
- struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
- u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
pdata->reg_shift;
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
- u32 val = (readl(pdata->phy_intf) & ~modemask) |
(modereg << pdata->reg_shift);- u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
SYSMGR_SOC64_EMAC0) >> 2;- u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
- int ret = socfpga_secure_reg_write32(id, val);
Use _update function, need read back and modify register. Similar to clrsetbits_le32().
- if (ret) {
dev_err(dev, "Failed to set PHY register via SMC call\n");return ret;- }
+#else
- clrsetbits_le32(pdata->phy_intf, modemask,
modereg << pdata->reg_shift);+#endif
- return 0;
+}