Signed-off-by: Alexander Stein alexander.stein@systec-electronic.com --- arch/arm/include/asm/arch-at91/hardware.h | 10 ++-- drivers/spi/atmel_dataflash_spi.c | 109 +++++++++++++++-------------- 2 files changed, 60 insertions(+), 59 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index f5f80e0..06ae26c 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -22,22 +22,22 @@ #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #include <asm/arch/at91sam9260.h> #define AT91_BASE_MCI AT91SAM9260_BASE_MCI -#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 +#define AT91_BASE_SPI AT91_SPI0_BASE #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #include <asm/arch/at91sam9261.h> -#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 +#define AT91_BASE_SPI AT91_SPI0_BASE #define AT91_ID_UHP AT91SAM9261_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9263) #include <asm/arch/at91sam9263.h> -#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 +#define AT91_BASE_SPI AT91_SPI0_BASE #define AT91_ID_UHP AT91SAM9263_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9RL) #include <asm/arch/at91sam9rl.h> -#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI +#define AT91_BASE_SPI AT91_SPI_BASE #define AT91_ID_UHP AT91SAM9RL_ID_UHP #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #include <asm/arch/at91sam9g45.h> @@ -47,7 +47,7 @@ #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91CAP9) #include <asm/arch/at91cap9.h> -#define AT91_BASE_SPI AT91CAP9_BASE_SPI0 +#define AT91_BASE_SPI AT91_SPI0_BASE #define AT91_ID_UHP AT91CAP9_ID_UHP #define AT91_PMC_UHP AT91CAP9_PMC_UHP #elif defined(CONFIG_AT91X40) diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 4a5c4aa..f325647 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -20,10 +20,7 @@ */
#include <common.h> -#ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! -#endif + #include <asm/arch/hardware.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> @@ -40,93 +37,96 @@
void AT91F_SpiInit(void) { + at91_spi_t *spi = (at91_spi_t *) AT91_BASE_SPI; + /* Reset the SPI */ - writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_CR_SWRST, &spi->cr);
/* Configure SPI in Master Mode with No CS selected !!! */ - writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, - AT91_BASE_SPI + AT91_SPI_MR); + writel(AT91_SPI_MR_MSTR | AT91_SPI_MR_MODFDIS | AT91_SPI_MR_PCS, + &spi->mr);
/* Configure CS0 */ - writel(AT91_SPI_NCPHA | - (AT91_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + writel(AT91_SPI_CSR_NCPHA | + (AT91_SPI_CSR_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_CSR_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(0)); + &spi->csr[0]);
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 /* Configure CS1 */ - writel(AT91_SPI_NCPHA | - (AT91_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + writel(AT91_SPI_CSR_NCPHA | + (AT91_SPI_CSR_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_CSR_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(1)); + &spi->csr[1]); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 /* Configure CS2 */ - writel(AT91_SPI_NCPHA | - (AT91_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + writel(AT91_SPI_CSR_NCPHA | + (AT91_SPI_CSR_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_CSR_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(2)); + &spi->csr[2]); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 /* Configure CS3 */ - writel(AT91_SPI_NCPHA | - (AT91_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + writel(AT91_SPI_CSR_NCPHA | + (AT91_SPI_CSR_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_CSR_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(3)); + &spi->csr[3]); #endif
/* SPI_Enable */ - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_CR_SPIEN, &spi->cr);
- while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS)); + while (!(readl(&spi->sr) & AT91_SPI_SR_SPIENS));
/* * Add tempo to get SPI in a safe state. * Should not be needed for new silicon (Rev B) */ udelay(500000); - readl(AT91_BASE_SPI + AT91_SPI_SR); - readl(AT91_BASE_SPI + AT91_SPI_RDR); + readl(&spi->sr); + readl(&spi->rdr);
}
void AT91F_SpiEnable(int cs) { unsigned long mode; + at91_spi_t *spi = (at91_spi_t *) AT91_BASE_SPI;
switch (cs) { case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_MR_PCS), + &spi->mr); break; case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_MR_PCS), + &spi->mr); break; case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_MR_PCS), + &spi->mr); break; case 3: - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_MR_PCS), + &spi->mr); break; }
/* SPI_Enable */ - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_CR_SPIEN, &spi->cr); }
unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); @@ -134,37 +134,38 @@ unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) { unsigned int timeout; + at91_spi_t *spi = (at91_spi_t *) AT91_BASE_SPI;
pDesc->state = BUSY;
- writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + writel(AT91_PDC_PTCR_TXTDIS + AT91_PDC_PTCR_RXTDIS, &spi->pdc.ptcr);
/* Initialize the Transmit and Receive Pointer */ - writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR); - writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR); + writel((unsigned int)pDesc->rx_cmd_pt, &spi->pdc.rpr); + writel((unsigned int)pDesc->tx_cmd_pt, &spi->pdc.tpr);
/* Intialize the Transmit and Receive Counters */ - writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR); - writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR); + writel(pDesc->rx_cmd_size, &spi->pdc.rcr); + writel(pDesc->tx_cmd_size, &spi->pdc.tcr);
if (pDesc->tx_data_size != 0) { /* Initialize the Next Transmit and Next Receive Pointer */ - writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR); - writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR); + writel((unsigned int)pDesc->rx_data_pt, &spi->pdc.rnpr); + writel((unsigned int)pDesc->tx_data_pt, &spi->pdc.tnpr);
/* Intialize the Next Transmit and Next Receive Counters */ - writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR); - writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR); + writel(pDesc->rx_data_size, &spi->pdc.rncr); + writel(pDesc->tx_data_size, &spi->pdc.tncr); }
/* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + reset_timer(); timeout = 0;
- writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); - while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && - ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT)); - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + writel(AT91_PDC_PTCR_TXTEN + AT91_PDC_PTCR_RXTEN, &spi->pdc.ptcr); + while (!(readl(&spi->sr) & AT91_SPI_SR_RXBUFF) && + ((timeout = get_timer(timeout)) < CONFIG_SYS_SPI_WRITE_TOUT)); + writel(AT91_PDC_PTCR_TXTDIS + AT91_PDC_PTCR_RXTDIS, &spi->pdc.ptcr); pDesc->state = IDLE;
if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {