From: Tien Fong Chee tien.fong.chee@intel.com
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@kernel.org Cc: Chin Liang See chin.liang.see@intel.com Cc: Tien Fong skywindctf@gmail.com --- Changes for V2 - Separate patch, reuse socfpga_common.h --- arch/arm/mach-socfpga/system_manager.c | 4 ++- drivers/fpga/socfpga.c | 7 +++-- include/configs/socfpga_arria10_socdk.h | 56 ++++++++++++++++++++------------- include/configs/socfpga_common.h | 33 ++++++++++++++++--- 4 files changed, 71 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 9e1c3fd..e1f0082 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2016 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,8 +11,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif
/* * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index bfefafd..7fd922e 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2016 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif
/* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) }
/* Prior programming the FPGA, all bridges need to be shut off */ - +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Disable all signals from hps peripheral controller to fpga */ writel(0, &sysmgr_regs->fpgaintfgrp_module); +#endif
/* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 577f60f..105c4c0 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Altera Corporation <www.altera.com> + * Copyright (C) 2015-2016 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0 */ @@ -8,31 +8,20 @@ #define __CONFIG_SOCFGPA_ARRIA10_H__
#include <asm/arch/base_addr_a10.h> + /* U-Boot Commands */ -#define CONFIG_SYS_NO_FLASH #define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE #define CONFIG_HW_WATCHDOG
#define CONFIG_CMD_ASKENV #define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MMC #define CONFIG_CMD_PING
-/* - * Memory configurations - */ -#define PHYS_SDRAM_1_SIZE 0x2000000 - /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" @@ -40,24 +29,30 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* - * Display CPU and Board Info + * U-Boot general configurations + */ +/* Cache options */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE + +/* + * U-Boot console configurations */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DOS_PARTITION + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x80000000
/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9031 - #endif
+/* + * U-Boot environment configurations + */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */ -#define CONFIG_ENV_OFFSET 512/* just after the MBR */
/* * arguments passed to the bootz command. The value of @@ -89,6 +84,23 @@ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ "bootm ${loadaddr} - ${fdt_addr}\0"
+/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> #endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f6a2f8d..6b26ea1 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -15,7 +15,9 @@ * High level configuration */ #define CONFIG_DISPLAY_BOARDINFO_LATE +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_ARCH_MISC_INIT +#endif #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS @@ -37,9 +39,13 @@ #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ +#endif #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ @@ -213,11 +219,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_NS16550_CLK 1000000 -#else +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS #define CONFIG_SYS_NS16550_CLK 100000000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS +#define CONFIG_SYS_NS16550_CLK 50000000 #endif #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -295,23 +304,39 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * SPL * - * SRAM Memory layout: + * SRAM Memory layout(TARGET_SOCFPGA_GEN5): * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_yyyy ...... Malloc area * 0xFFFF_zzzz ...... Global Data * 0xFFFF_FF00 ...... End of SRAM + * + * SRAM Memory layout(TARGET_SOCFPGA_ARRIA10): + * + * 0xFFE0_0000 ...... Start of SRAM + * 0xFFE0_xxxx ...... Top of stack (grows down) + * 0xFFE0_yyyy ...... Malloc area + * 0xFFE0_zzzz ...... Global Data + * 0xFFE3_FFFF ...... End of SRAM */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SPL_MAX_SIZE (64 * 1024) +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#endif
/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#endif #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #else #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1